Engineer Design

Jeff Eichel

* ******** **., ******** **. ***** *******@*****.*** Cell 978-***-****

http://www.linkedin.com/in/jeffeichel

HARDWARE ENGINEER

Highly experienced hardware engineer. Proficient in all phases of development of high volume electronic products. Excellent in communicator of technical information and all aspects of chip and board development and test. Superior problem solving skills. Created simulation test benches and synthesis scripts to help debug and logic and netlist problems by analyzing results. Excellent at communicating technical information to customers, management and co-workers. Known for integrity, on time delivery, enjoying a challenge, fostering team spirit across cultures and organizations and also continuous improvement. Documented design procedures for reuse by other engineers. Aided supervisor in communicating with off-shore consultants.

AREAS OF EXPERTISE

Verilog/VHDL language and simulation, synthesis, STA, DFT, TCL, Conformal LEC, SPICE. Signal integrity. Oscilloscopes and Logic Analyzers. Technical liaison between company and customer.

PROFESSIONAL EXPERIENCE

eInfochips Inc Sunnyvale, CA. 2012-Present

Independent contractor. On site at Toshiba’s office in Marlboro MA.

Creating at-speed mass production scan vectors for 65 nM telecom ASIC.

Toshiba America Electronic Components 1996 -2012

Subsidiary of one of the largest semiconductor producers in the world. Design center for development of

State of the art custom SoCs/ASICs. ISO 9000 and 14000 certified.

SR.STAFF DESIGN ENGINEER, Toshiba, Marlboro, MA.

Technical point of contact between Toshiba and customers developing deep submicron ASICs for their products. Hired to make technical pre-sales presentations and handle all post-sales customer questions and challenges. Became DFT expert.

* Coordinated sign-off activities.

* Interfaced with other internal groups, Japanese colleagues, off-shore consultants, customers.

* Test vector extraction from functional test benches.

* State of the art scan and membist insertion.

* Stuck-at and at-speed ATPG test vector creation.

* Simulation, debug verification of test vectors.

* Resolving problems arising in mass-production.

* Six Sigma training.

* Cross cultural communications training.

Jeff Eichel *******@*****.*** 978-***-**** page 2

UB Networks 1989 – 1996

Innovator of Ethernet on Twisted Pair and Networking Hubs

Design Engineer, Andover, MA.

Designed, developed, supported chip and board level networking products.

* Implemented network accessible “DOS Engine”

* Designed logic to improve functionality of proprietary interface IC.

* Helped resolve problems arising in mass production of network interface cards.

* Writing specifications for, designing, productizing high-value, highly reliable, low cost networking products.

* Wrote test benches to verify functionality of ASICs from which production test vectors were extracted.

* Created RTL for, synthesized, developed FPGAs used to test and evaluate new products.

* Learned verilog and Synopsys Design Compiler.

New York University 1984 – 1989

Assistant Research Scientist, Courant Institute of Mathematical Sciences

Designed and debugged hardware for for experimental MIMD parallel computers used as vehicle for

research in parallel programming.

* Implemented new memory system using megabit DRAMs

* Added floating point coprocessor.

* Implemented logic reduction using programmable logic.

* Helped design AMD 29K RISC based CPU board.

* Supervised technicians and student engineers.

PRIOR TO 1984

Roles included development of factory and warehouse automation products, and military microcomputer, communications and ATE products. Worked with industrial programmable logic controllers, UARTS, Intel and Motorola microprocessors, IEEE 488. Mini and microcomputer interfaces, AMD 2900 bit-slice hardware and microprogramming, assembly and high level language programming.

Organizations included Supreme Equipment and Systems, Brooklyn NY; ITT, Nutley NJ; Lockheed Electronics Corp, Plainfield NJ; Harris Corp. PRD Division, Syosset, NY

EDUCATION

MSEE, Polytechnic Institute of NY. Brooklyn, NY

BEE, Pratt Institute . Brooklyn, NY.

AAS/ET, Queensboro CC, NY

Various graduate level and Continuing Ed. classes post Master’s degree.

Feb 2010 – Currently pursuing MS in Virtual Team Management and

Present Communication at Brandeis Univ. Degree expected June 2015.

Teaching Taught several undergraduate engineering and computer science

classes at Pratt Institute and New York University.

Programming C, C++, PL/1, Assembly, Microprogramming, PERL, TCL.

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