Design Training

Amit Kumar

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Email : ***********.**@*****.*** Mob.: +91-720*******

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Objective:

Seeking an opportunity to work with a reputable firm that provides a conductive environment and my educational skills effectively enables me to make a positive contribution towards the growth of the company and also where I can enhance my skills.

Academic Qualification:

Course Institution

Board /University Year of Completion Aggregate (%)

B.Tech. (ECE) M.I.E.T.

Meerut UP UPTU Lucknow 2011 67

12th Board P.V.P. Inter College Baraur UP State Board 2006 72

10th Board P.V.P. Inter College Baraur UP State Board 2004 67

Maven Silicon Certified Advanced VLSI Design and Verification Course (VLSI – RN ) from Maven Silicon VLSI Design and Training Center, Bangalore.

Skills: Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and Verification

VLSI Domain Skills

HDLs: Verilog

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification

EDA Tool: Modelsim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Good knowledge : RTL Coding, FSM based design, Simulation,

VLSI Projects :

Real Time Clock – RTL design and verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Real Time Clock using Verilog HDL independently

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

UART- IP Core – Verification

HVL : System Verilog

EDA Tools : Modelsim, Questa – Verification Platform.

The UART IP core consists of a transmitter, a receiver, a modem interface, a baud generator, an interrupt controller, and various control and status registers. This core can operate in 8-bit data bus mode or in 32-bit bus mode, which is now the default mode. It is an interface between wishbone compatible UART transceiver, which allow communication with modem or other external devices, like another computer using a serial cable and RS232 protocol. The UART core RTL is technology independent and fully synthesizable.

Academic Project :

Prepaid Energy Meter

Description: Prepaid energy meter consist of a microcontroller like(cpu),power supply unit ,display unit(which displaying voltage ,current and remaining balance), indicator(buzzer) which indicate before finishing the balance and a keyboard by which customer recharge their meter.In this we create some tariff voucher by using which we recharge the meter

Training, Certification & Seminars Attended:

Completed Industrial Training in “KHF 1050 communication system” in Design Department of HAL TAD Kanpur.

Attend a workshop on “Recent Trends in Image Processing” organized by School Of Electronics Engineering.

Co-curriculum Activities

Co-ordinator of technical committee(Electronics) in college fest.

Member of society of electronics engineering(committee in college).

Participate in athletics & badminton competition.

Personal Profile

Date of Birth : 25-Sep-1989

Gender : Male

Father name : Mr. Pramod Kumar

Mother tongue : Hindi

Nationality : Indian

Marital Status : Unmarried

Languages : English, Hindi

Hobbies : Travelling, Playing vedio games

Permanent Address : Vill- Keshi Ka Purwa,

Post- Baraur,

Dist- Ramabai Nagar - 209312

I hereby declare that the above information's are true to best of my knowledge.

PLACE: Bangalore Amit Kumar

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