Engineer Design

Ark-Chew Wong

** ******** **** *****: 949-***-**** begin_of_the_skype_highlighting              949-***-****      end_of_the_skype_highlighting

Irvine, CA 92606 Home Phone: 949-***-****

Email: ********@*****.***

SUMMARY:

• Experienced design engineer seeking a position in the area of analog/mixed-signal IC and systems.

PROFESSIONAL EXPERIENCE:

Beceem Communications., Irvine, CA April 2010- Present

Senior Staff Analog/Mixed-Signal Design Engineer

• Designed and implemented analog/RF/mixed-signal circuit blocks for Wimax and LTE applications:

 High speed 6-phase DLL and delay line for 2G/3G interface in 40nm LP CMOS technology.

 LO generation circuitry for Wimax/LTE TX and RX front ends in 65nm CMOS technology. Circuitry in LO generation path includes mux selector and CML driver buffers and divide-by-2 circuit.

 Master bias generator circuit in 65nm CMOS technology.

 Pad ring and I/O for ESD protection with optimum noise performance and isolation.

 Reviewed specs for MPHY TX and RX lanes for 2G/3G applications.

Broadcom Corp., Irvine, CA 2007-2010

Senior Staff Scientist

• Analog/mixed-signal circuits for ethernet applications:

 Linedriver for 10BT/100TX/1G.

 Passive termination and hybrid circuitries for full and half duplex ethernet applications.

 High speed ADC and miscellaneous RX-chain blocks.

 I/O protection for cable ESD.

 2ns delay DLL.

• Chip lead for the following projects:

 Cost-reduced transceiver in 65nm technology for 100TX/10BT applications. Led a 5-men team in the analog system level partitioning, design, and layout of the transceiver. Was actively involved in the measurement and characterization of the IP. Current IP is used in several SOCs being sampled, or going into full production on several switch and networking products.

 High speed ADC in 40nm CMOS technology. Led a 3-men team in the brainstorming, design and simulation, layout, and characterization of this ADC. This ADC is currently being used and experimented in a few 40nm IPs.

Skyworks Solutions Inc., Irvine, CA 2004-2007

Senior Design Engineer

• Designed analog and mixed-signal blocks for CDMA and EDGE applications in 65nm:

 High order RC filter with successive approximation dc offset cancellation for time-based systems.

 Current steering DACs with static randomization for WCDMA baseband analog interface.

 Continuous time smoothing filter for WCDMA application.

 UHF VCO buffer and bidirectional buffers for operation at 4GHz for EDGE application.

 High resolution PA control DAC.

 Designed blocks for a CT ADC for WEDGE application. Participate in some system level partitioning.

• System level modeling and simulation of analog and mixed-signal baseband using VHDL, MATLAB, and Simulink.

Conexant Systems/GlobespanVirata Inc., Irvine, CA 2002-2004

Analog Design Engineer

• Designed and implemented analog IC blocks for VDSL CO and CPE AFE chips:

 RX front-end programmable gain amplifier.

 Continuous time active filters for CO and CPE applications.

 High resolution digital-to-analog data converters for transmit path.

• System level simulation of VDSL analog front ends for CO and CPE applications.

• Participated actively in lab measurement and characterization of these analog front ends.

Mindspeed Technologies, Newport Beach, CA 2001-2002

Analog Design Engineer

• Designed analog and mixed-signal integrated circuits for optical & SERDES applications:

University of Michigan, Ann Arbor, MI 1995-2001

Graduate Student Research Assistance

MEMS For Wireless Communications

• Graduate research work in the design, fabrication, measurement and characterization of surface and bulk micromachined resonators, filters, and mixers for wireless communication applications.

Austria Mikro Systeme, Graz, Austria Summers 94 & 95

Design Support Group, Intern Engineer

• Established methodology for characterization and testing of 8, 10 and 12 bits ADCs and DACs. fabricated using a 0.8m in-house BiCMOS process.. Performed extensive testing and study of digital-analog and analog-digital data converters, and interface circuitry.

EDUCATION:

University of Michigan, Ann Arbor

Ph.D. in Electical Engineering and Computer Science. Graduated: July 2001

Dissertation Title: VHF Microelectromechanical Mixer-Filters

Advisor: Prof. Clark T.-C. Nguyen (currently at UC Berkeley)

The Johns Hopkins University

Master of Science in Electrical Engineering. Graduated May, 1995

Bachelor of Science in Electrical Engineering. Graduated May, 1994

SOFTWARE EXPERIENCE:

• Experienced with Cadence SpectreRF, APS, and Ultrasim simulators.

• Experienced with using Cadence and LEDIT layout tools.

• Experienced with MATLAB and Simulink.

HONORS:

• Recipient of the Roger A. Haken Best Student Paper Award at the 1998 International Electron Devices Meeting, December 1998, for paper titled: Micromechanical Mixers+Filters.

• Co-recipient of the Best Student Paper and 1st Place in the Conceptual Design Category at the Design Automation Conference 2000, for paper titled: An Integrated MEMS-BiCMOS SINCGARS Transceiver.

• Graduate Research Assistantships, University of Michigan, Ann Arbor (1995-2001).

• The Johns Hopkins University, Whiting School of Engineering Dean’s List.

• Graduate Student Fellowship, The Johns Hopkins University (1994-1995).

PUBLICATIONS:

• Nine IEEE conference papers and four IEEE journal paper pertaining to the areas of MEMs, and Circuits merged with MEMs technology.

PATENTS:

• United States Patent 6,569,754, Method for makng a module including a microplatform.

• United States Patent 7,642,946 Successive Approximation Analog to Digital Converter.

• 3 other patents pending related to linedrivers for fast ethernet applications.

• Applications for 2 other patents related to cable ESD in progress.

PROFESSIONAL AFFILIATIONS:

• Institute of Electrical and Electronics Engineers (IEEE)

• Tau Beta Pi Honor Society (Engineering Honor Society)

• Eta Kappa Nu (Electrical Engineering Honor Society)

REFERENCES: Available upon request

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