Semiconductor Product Engineer
Resume:
DEEPAK BHARADWAJ
Emeryville, CA-*4608
********@*****.***
OBJECTIVE: Seeking an opportunity in Electrical and Computer Engineering where I can utilize my technical skills and experience to help achieve organizational goals.
Summary of Qualifications
5+ years of experience in Product Engineering of a memory based Semiconductor Company. Experience on DRAM and NAND flash based memories. Extensively worked on Silicon and packaged parts. Worked with probe, test and fab engineers in qualification of memory products. Great Team member with outstanding analytical and technical skills.
WORK EXPERIENCE:
Micron Technology Inc, Mar 05-Mar 09: Product Engineer – MPG Product Engineering:
1. Involved in design validation, Silicon debug, characterization qualification and failure analysis of NAND Flash Memory and Dynamic Random Access Memory (DRAM) devices.
2. Worked on part design and analyzing fail modes on various memory parts: DDR2, DDR3, NAND FLASH memory. Developed new repair algorithms based off test or customer rejects.
3. Responsible for developing and optimizing existing probe tests into absolute consistent coverage for known and new failure modes to maximize backend yield, minimize probe loss through overkills and at the shortest possible pattern times.
4. Worked with Design, Probe and Test engineering for recommendation of test methodologies and screens for various designs.
5. Worked extensively with Probe engineers on NEXTEST,ADVANTEST and TERADYNE ATE testers: to fan out and train them on newly developed test patterns, solving issues on probe patterns and on test time reduction.
6. Well versed with the use of tools such as FIB, SEM, Dual Beam, IREM, and AFM for physical failure analysis (PFA).
7. In-depth knowledge of logic design and thorough understanding of circuits at gate level used in the memory parts.
8. Supported the ramping of parts in the 300mm fabs for volume production and thereby monitored various yield issues by identifying trends and patterns in production data. Familiar with complex data extraction from all steps (Probe, Parametric and backend test steps), so as to correlate known fail modes to process, parametric, repair, probe, test and reticle using Jump, Excel and data mining tools using Perl.
9. Responsible for writing and supporting APG projects for DRAM parts .Also wrote APG codes looking at the Ambyx codes to correlate backend fails of the BURN tests. Involved in designing tests/screens to accelerate these fails and catch them earlier at probe.
10. Performed Verilog, Hspice and Hsim simulations to verify chip design functionality, compression, and testmode logic. Also performed analog/digital signal micro-probing on silicon to verify part timing and debug part issues. Familiar with the use of DF2 and K2 schematic and layout databases.
11. Worked with Yield Engineers (YE) and Fab engineers to help them electrically characterize fails. Proficient in bench testing and characterization using oscilloscopes, Spectrum and logic analyzers, Keithley instruments.
Intern Engineer: Jun 04-Aug04 –Micron Technology FAB 4 YE.
Involved extensively in physical failure analysis of 512Mb DRAM wafers from probe .Also did electrical failure analysis for certain special work requests (SWR).
Graduate Research Assistant: Oct 03-Feb 05-Fiber and Integrated Optics Lab, Dept of Electrical and Computer Engineering, University of Arizona.
-Involved in the design of Integrated Optic Chip to be used for Dispersion Compensation-Masters Thesis.
Graduate Research Assistant: Nov 2002-Oct 03 -Laboratory for Nanotechnology, Optical Sciences Center University of Arizona.
-Measured Work Function of various materials using Kelvin Probe Force Microscopy to be used in the development of Nanoscale CMOS Chemical Sensors.
EDUCATION:
The University of Arizona, Tucson, AZ
Master of Science (M.S) in Electrical and Computer Engineering, Mar 05
Cumulative GPA 3.556/4
Related Courses:
Digital VLSI design system, Analog CMOS IC Design, Semiconductor processing, Digital Electronic Techniques, Surface Science, Electronic Devices and Circuits, Optical Communications, Digital Signal Processing, Object Oriented Simulation of Discrete Events, Fundamental of Computer Networks,
Karnatak University, India
Bachelor of Engineering in Electronics and Telecommunication, Nov 2000
Cumulative GPA 4.0/4.0
KEY PROJECTS:
Designed a 10-bit R-2R DAC using TSMC’s 180 nm (CM018) process and a VDD of 1.8 V (Dec 2007) - The OPAMP designed for this application had a settling time of 8ns and the error in linearity when compared to an ideal opamp was ~ 16-20mV. Power dissipation of the circuit was 9mW. The opamp was designed to have a higher gain due to the application.
Designed an optical Communication Link of 5000Km operating at 400 Gb/s with a BER of 10-16 (Nov2003-Dec 2003)
-Did necessary calculations and selected various parts for the link.
Interfaced Altera PLC with a Keyboard (Mar2002-May2002)
-using AHDL
COMPUTER SKILLS:
ATE Testers: Advantest, Teradyne
Languages: C, C ++, Java, FORTRAN, Pascal, ALP-8085, 8086
CAE Tools: PSPICE, MATLAB, Magic, AHDL, Lab view, Mathematica, Optonex, Nextest, Micromate
Statistics: JMP, Excel
Platforms: UNIX, MS DOS, Sun Solaris, MS Windows
REFERENCES:
Available upon request
Authorized to Work in United States (EAD)
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