Software Engineer / Developer

RESUME

Rashmi Ranjan Sahu

S/O Shri Niranjan Sahu

Jayadurga nagar

Berhampur-10

Orissa

Email id: - ************.******@*****.***

Cell no: - 096********

CAREER OBJECTIVE: - Seeking a position to utilize my skills and abilities in an organization that offers professional growth while being resourceful, innovative and flexible.

EDUCATIONAL QUALIFICATION:-

QUALIFICATION BOARD/UNIVERSITY AGGREGATE MARKS

B.TECH(ECE) B.P.U.T 7.48(CGPA)

12Th C.B.S.E 73.4%

10Th C.B.S.E 78.6%

SOFTWARE EFFICIENCY:-

Languages: - C, C++, VHDL

COURSES:-

Programming in Advance ‘C’ from Lakshya, Berhampur

Very large scale integration design from Central tool room and training center, Bhubaneswar

SEMINARS AND WORKSHOPS:-

Participated in “Scintillations-2010”, a workshop on “VLSI & Embedded System” conducted by RIT Berhampur

Participated in “Cognizance-2K8” conducted by Electronics & communication Society, RIT Berhampur and ISTE students chapter

Presented a technical paper on “BCD adders and their reversible logic implementation for IEEE 754r”

PROJECT:-

“BCD adders and their reversible logic implementation for IEEE 754r”

PROJECT DESCRIPTION:-

. This project proposes two novel BCD adders called carry skip and carry look-ahead BCD adders respectively.

Furthermore, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this project provides the reversible logic implementation of the conventional BCD adder as the well as the proposed Carry Skip BCD adder using a recently proposed TSG gate. Furthermore, a new reversible gate called TS-3 is also being proposed and it has been shown that the proposed reversible logic implementation of the BCD Adders is much better compared to recently proposed one, in terms of number of reversible gates used and garbage outputs produced. The reversible BCD circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU.

ACHIEVEMENTS:-

Participated in National Youth Parliament competition at regional level conducted by KENDRIYA VIDYALYA SANGATHAN at Kendriya Vidyalaya ARC ,Charbatia

Awarded a consolation prize in the event PIPTRONIX held in the COGNIZANCE-2K8 conducted by Electronics & communication Society, RIT Berhampur and ISTE students

chapter

.

PERSONAL SKILLS:-

Comprehensive problem solving abilities, excellent verbal and written communication skills, ability to deal with people diplomatically, willingness to learn team facilitator hard worker.

PERSONAL PROFILE:-

NAME: - Rashmi Ranjan Sahu

FATHER’S NAME: - Niranjan Sahu

MOTHER’S NAME: - Jhunu Rani Sahu

NATIONALITY: - Indian

DATE OF BIRTH: - 23-07-1988

HOBBIES: - learning new things from any resource I get

LANGUAGES KNOWN: - English, Hindi, Oriya

DECLARATION

I here by declare that the above statement furnished is true to the best of my knowledge and belief.

Date: Yours sincerely

Place:

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