Circuit Design Engineer
Resume:
CIRCUIT DESIGN ENGINEER
Superior record of steady career progression in CMOS IC Industry, mirrors underlying commitment to deliver robust, customer-responsive design services and projects in deadline- and task-driven environments. Create an environment oriented to trust, open communication, creative thinking, and cohesive team effort. Maintain healthy group dynamics. Commonsense approach and "big-picture" vision are hallmarks of a consensus-driven leadership style that encourages problem ownership and empowers staff to brainstorm solutions. Respected for troubleshooting acuity and capacity to think "outside the box" for more effective outcomes. Independent work habits, intuitive business sense, and an instant grasp of new technologies underpin dedication to steer streamlined operations within a cost-effective and productive semiconductor IT function.
SUMMARY OF QUALIFICATION
• Extensive experience of the Full & Semi Custom Circuit Design in the CMOS and SOI/CMOS technology up to 22nm process with 4GHz high speed frequency, Chip Architecture, Floor Plan, Digital/Analog Design, Design Verification, Timing Analysis, Full Chip Design Simulation, Physical Design, VHDL code conversion for the new project, and Design team lead for + 8 years
• Outstanding achievement in the Device Failure Analysis on the wafer and package level, Characterization, Test Methodology development, Test code programming, successful Product Development transfer to the Mass Production and Customer System, Long-Term Product Planning and Project Management for + 12 years.
• Led teams or teamed with the members to successfully develop 1Gb DDR2, 1Gb DDR, 4Mb/128Mb SDRAM, 256Mb RLDRAM, 64Mb/256Mb PSRAM, 8Mb SGRAM, 9Mb DCAM, 256Mb/1Gb RAMBUS DRAM/XDR, 64Kb/1Mb SRAM, and L2 Cache SRAM Array with up to 4GHz high frequency, 32/22nm SOI CMOS technology.
• Studied Verilog HDL Design and RTL coding for the Complex Digital System at North Carolina State University in 2009.
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EMPLOYMENT NARRATIVE
IBM Rochester, MN 2010 - Current
Circuit Design Engineer
1) Working on Static / Dynamic circuit design for L2 Cache SRAM and Design Verification in the 32nm and 22nm SOI CMOS Technology with 4GHz high speed frequency.
2) Analyzed Dynamic circuit behavior with keeper and pull-down TR ratio on the critical data out path with pre-charge scheme to meet the 32nm technology performance in the beginning of the project stage by using Power-SPICE and checked power targets by using circuit sizing skills and knowledge of transistor properties to change device dimensions.
3) Designed and simulated the Clock pulse expansion and control circuits for word line and pre-charge pulse expansion control with Level shifter circuits up to 4GHz high frequency by using Power-SPICE.
4) Developed verification methodology for transistor level circuit to ensure match to logic description in terms of desired functionality using knowledge of circuit design, logic/timing simulation and debugging skills.
5) Analyzed and debugged timing analysis and functionality of the customer SRAM array using Ultra-SIM.
6) Worked on the Logical Equivalent Check verification using Verity comparing VHDL model VS schematic and TPGTECH. Generated the correspondence, constraints, device-markup files. Debugged and solved Verity and TPGTECH problems.
7) Worked on VHDL code conversion for the new project from the previous and verified VHDL code through Logic Equivalent Check after changing circuit.
8) Designed and simulated the cross section circuit with coupling noise model.
9) Generated SKILL code for converting the master cell book to the custom macro cell.
10) Used TCL and Perl script to generate and modify correspondence points for running Logic Equivalent Check.
11) Worked on layout verifications, DRC, LVS, physical block layout, schematic migration and Ultrasim set-up for new project Full Chip simulation.
QIMONDA Cary, NC 2007 - 2008
Staff Design Engineer / Team Lead
1) Successfully launched 1Gb DDR2 DRAM Design project with up to 1GHz frequency for 70nm CMOS Trench process to the manufacture and customer systems.
2) Re-designed and evaluated the memory core array cross-section to 2Mb from 1Gb array in order to develop a lower VDD core circuit up to 1.2V by using TITAN simulation. Implemented accurate and simplified array core model with the array control circuits and the Bit Line Sense Amp blocks.
3) Designed and evaluated the data output cross- section with DLL voltage generator block in order to solve tDQSCK shift/jitter, CAS Latency shift problem. Created specific Full chip simulation stimulus exposing a weak timing on the CAS Latency control related to DLL voltage fluctuations with the Power Down mode.
4) Designed and simulated the Data I/O HSPICE model with OCD and ODT circuits. Designed a simplified data I/O HSPICE model in order to create the fastest I/O model for the system level simulation.
5) Evaluated and proposed a 70nm CMOS technology for a new Cu metal process for the next generation of 1Gb DDR2 by using RCX simulation with the modified new model parameter. Analyzed the full chip architecture and floor plan for improving device speed timing on the new process.
6) Simulated and analyzed block circuits including Analog circuits, Voltage Reference, Regulator for debugging design circuits.
7) Planned and developed the Full Chip Design Verification Simulation codes for NANOSIM, Verilog on EPIC for 1Gb DDR2 and 1Gb XDR. Analyzed and prepared the full chip architecture of 1Gb XDR for the full chip Design Verification.
8) Coordinated and led the technical meeting for design, yield improvement, and customer system failure return issues.
9) Made and presented the design review, project status, and failure analysis reports. And supported PE/AE group for the technical issues related to device failures on component and customer system level and yield improvement.
MICRON Technology Boise, ID 2002 - 2007
Product/Database Design Engineer
1) Worked on the full chip simulation, Design circuit debug, Schematic revision, Process Split experiment, Device Failure Analysis on package and wafer level, Test Yield improvement, and Process Control Monitor data Analysis with Characterization data, Test data, Yield data by using JMP for 64Mb/128Mb PSRAM, 256Mb RLDRAM, Low power 128Mb SDRAM.
2) Revised Circuits and Layouts for tape-out through Full Chip Simulation debug and Device Failure Analysis.
3) Managed the schematic and layout GDS data base control. Worked on the physical layout, Layout Verification with DRC/LVS/HCOMPARE, controlled and fixed Metal fill/Fracture data for 256Mb PSRAM, 128Mb, 256Mb, and 512Mb SDRAM/DDR DRAM.
4) Analyzed and debugged the internal signals on HSIM and NANOSIM and p-probing for 256Mb RLDRAM and 128Mb SDRAM.
5) Analyzed a Latch-up problem on 128Mb SDRAM qualification stage by using EMMI analysis and solved by adding the guard-ring contacts surrounding the internal voltage generators.
6) Analyzed the low voltage performance with variety of circuit problems, which were a write back margin and data sense amp clock timing problem at high frequency, process variation for 128Mb SDRAM by using FIB experiment on the second data sense amp clock tuning.
7) Solved the Input Leakage problem by analyzing PCM data and experimented the process Halo implant dose and angle split.
8) Analyzed and verified BIST test of the 1st silicon and evaluation run for 64Mb/128Mb PSRAM, 256Mb RLDRAM, Low power 128Mb SDRAM.
MOSAID Technology Ottawa, Canada 2001 - 2001
Sr. Product Engineer
1) Set-up and Generated Back-End Test Base Line specification, Back-End Electric Test Specification, Laser Repair Specification for the redundancy cell repair, Package Burn-In Test specification for 9Mb DCAM Test Manufacture
2) Set-up Characterization, Design Debug, and Failure Analysis plans including probe card, test board preparation for 9 M DCAM
3) Coordinated the related departments and the 3rd parties for test manufacture setup for 9Mb DCAM.
HYNIX Semiconductor Ichon, Korea 1989 - 2001
Principal Design and Product Test Engineer/Manager
1) Led up to 3 teams of 8 or 24 engineers to design and develop 128Mb/16Mb/4Mb SDRAM for up to 0.18um CMOS technology, which were successfully launched in Manufacture and Customer Systems.
2) Designed the robust Chip Architectures and Floor Plans according to the variety of the process technology for 128M, 4M SDRAM, which had over 69% wafer test yield hit for the 1st silicon.
3) Designed and simulated the memory core array, full chip, column address path with the burst length and CAS latency control for improving Data I/O access time for 8Mb SGRAM, 4Mb, 128Mb SDRAM up to 0.18um process technology.
4) Designed and simulated the Memory Core Array Cross-Sections simplifying Bit Line Sense Amp blocks, Secondary Data Sense Amp blocks, the final Column address decoder blocks, and array control blocks for 4Mb, 128Mb SDRAM.
5) Designed and simulated the differential amplifier-based Data Input buffer, Output buffer controlled by pipe line control for CAS latency and Burst length control and I/O path to improve the Setup and hold time, data access time, current consumption for 4Mb and 128Mb SDRAM.
6) Designed Data I/O HSPICE with X1, X4, X8, and X16 mode and IBIS Model for 128M, 4M, 8M SDRAM.
7) Created the Full Chip Design Verification plan and Full Chip Simulation Stimulus for HSIM and NANOSIM for 8Mb SGRAM, 4Mb, 64Mb, and 128Mb SDRAM.
8) Planned Design Projects, Generated and presented Design Documentations.
9) Device Failure Analysis on wafer and package level for 64Kb, 256Kb, 1Mb SRAM and fast SRAM using FIB, SEM, EMMI, IDS5000, ANDO 8042/45 ATE system, and MOSAID MS3480 system for I/O Leakage/Stand-by/Operation current problems, Timing, Noise Immunity related to Power & Function problems.
10) Analyzed the internal signal timings by using u-probing on HP4145 measuring the Transistor characterizations, saturation current, threshold voltage, break-down voltage, oxide break-down time, etc for SRAM device.
11) Worked on Plastic package de-cap for SEM analysis, FIB experiments, and internal signal probing for SRAM/SDRAM products.
12) Analyzed the low yield and device failures by using a statistical software tool, IDS with the Yield data, Process Control Monitor data, wafer/package test data, and characterization data.
13) Led the process split experiments for improving the device functionality performance and yield improvement for SRAM and SDRAM.
14) Led and coordinated Design, Product, and Process Engineering teams / Package & Test Manufacture and OEM 3rd Parties in German, Taiwan, & Singapore for the Project development and Audit.
15) Planned and generated the Back-end Test base line spec, Wafer Probe/Package Test spec, Characterization specification and wrote the program codes on ANDO 8042/45 and Teradyne J937 ATE systems for 64Kb, 256kb, 1Mb SRAM.
16) Significantly reduced the test production cost by + $100s million and the package product procedure from 3 step tests (300% test) to 2 step tests (200% test) for all SRAM production by developing a test condition.
17) Sustained the package test production for 16Kb and 64Kb SRAM manufactures.
18) Planned a Wafer Level Burn-In Test procedure and led the wafer level Burn-In project.
19) Planned Long-Term Strategic Product Road Map and led the Product Planning Team.
Analyzed competitors, new technology, and application trends in the markets.
Conducted company-wide meeting for deciding the long-term product plan and goal.
Generated and proposed the new device spec and products to the customers
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EDUCATION
1) B.S., Electronics Engineering
Kyung-Hee University, Seoul, Korea
2) Verilog HDL Design of Complex Digital System, Certificate
North Carolina State University, Raleigh, NC
SKILLS
Circuit Design & Layout tools ATE & Failure Analysis tools Software
1. Cadence Virtuoso (Df2, OPUS), Power-SPICE, HSPICE, HSIM, TITAN, NANOSIM, Verilog, VHDL
2. DRC, LVS, HCOMPARE
3. k2view, vcats, GDS data steam out/ data base control for tape-out
4. Verity/TPGTECH Logic Equivalent Check for Design verification 1. HP4145, IDS5000, EMMI, IREM, LCD, SEM, FIB experiment, Logic Analyzer, Oscilloscope
2. u-probe station and pico-probing
3. ATE system: ANDO8042/45, J937, MOSAID test system 1. JMP and IDS for Process Control Monitor (Keithley) data /Test/Characterization data analysis
2. Perl, C, UNIX, and MS-Office Suite (Word, Excel, Power point, and outlook)
PATENT
• Cell Plate Voltage Generator of a Semiconductor Memory Device. (U.S. Patent No. 6,081,459)
REFERENCE
• Available upon request
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