Asic / Fpga / Rtl Design Validation, Verilog, Vlsi, Vhdl, CAD, Verific

OBJECTIVE: Seeking Full time position in Computer Engineering-Hardware, ASIC/FPGA/RTL design or validation.

EDUCATION

Master's of Science in Computer Engineering (Hardware) (Expected Graduation-May’12)

Syracuse University, Syracuse, NY, USA.

Bachelor's of Technology in Electronics and Communication Engineering,

Kurukshetra University. (Graduated-June’08)

TECHNICAL SKILLS

Hardware Descriptive Languages : Verilog HDL, VHDL.

Programming Languages : C, C++.

Operating Systems : Windows, Unix.

IDE’s : Cadence tools (Virtuoso Layout & Schematic editors, Spectre), Simulink,

Xilinx, TetraMaxATPG, Visual Studio-2008/2010.

WORKING EXPERIENCE

Worked as a Software Developer in VB.Net in Seasia Consulting from July 2008-December 2008.

As a Trainee Sales Manager in FCS from January 2009 – March 2009.

Part time as Consultant in The Shapers from April 2009-December 2009.

ACADEMIC PROJECTS

Generating VLSI Layout for Cadence (Fall 2011)

• Boolean Expression is given as an Input.

• The tool will automatically generate a Netlist and layout in ASCII format.

• Output will be Optimum Layout with Left-Edge algorithm applied to it.

• Layout is with Minimized Metal Layers with complete Design Rule Checking(DRC). All this is done using C++.

• ASCII format is converted to GDS2 format for viewing it in layout generator tools like cadence.

Placement and Routing in VLSI using C++ (Fall 2011)

• Using the Gordian method of Cell placement the position of cell is calculated and the interconnections between them at different stages using C++.

• The input is a text file(.txt) which provides the information of the number of nets, both movable and fixed, the number of cells and their connections to other cells.

8-bit Micro Processor (Fall 2010)

• Step by Step implementation of the components of a processor.

• Components are Full adder transformed into an 8-bit ALU, four 8-bit Registers, Instruction Register and a Program Counter.

• Functions performed are SHL, SHR, ADD, SUB, JUMP, HOLD, and COUNT.

• Components were developed as combinational logic.

• The Verilog Code for the controller(FSM with 17 states) and Test Bench were written in VERILOG and then its layout was generated using code in Cadence.

• The entire design was implemented in Cadence Virtuoso with the size of Layout Minimized.

Implement 16-bit Processor using VHDL (Fall 2010)

• Execute the instruction set like MOVE, ADD, SUB, JUMP.

• Each module input and outputs configured to fulfill the correct execution of all instructions.

• Used the Xilinx FPGA platform. The values of IR, reset, clock and Memory address were calculated.

XML Metadata Manager

• This Project stores and retrieves files from the repository. Each package held by the repository with an XML file containing file metadata.

• Uses "Multimap" as a data structure for storing filenames(.h and .cpp) inside the package.

• Analyzed dependency between files and build XML metadata files that contains the name of the file's package and the files and the packages on which it depends.

RELAVENT COURSEWORK

• CAD (Used: C++)

• Digital Machine Design(Digital Logic Design)

• VLSI Timing Analysis

• CMOS VLSI Design

• VLSI Testing and Verification

• Power Issues of VLSI Design(Low Power Design Issues of VLSI)

• Hands on FPGA.

• Object Oriented Analysis & Design

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