Manager Engineer
Resume:
RACHID BOURAOUI
**** ******* *****, ***. ****, Milpitas, CA 95035
Email: ******.********@*****.***
Tel: 707-***-****
SENIOR DIGITAL ASIC/FPGA ENGINEER
Engineering professional well-versed in ASIC/FPGA Design with a wide range of experiences covering all facets of the sub-micron chip design cycle, ranging from Architectural definition, to HDL Coding, Synthesis and Testbench generation. Up-to-date knowledge of the latest development in telecommunications and data communications industries. Excellent analytical and problem-solving ability, an active team player, and a highly motivated self-starter. Awarded Ph.D. Degree in Microelectronics with Honor.
TECHNICAL SKILLS
Operating Systems: Unix and Windows
Hardware Languages: SystemVerilog, Verilog and VHDL
CAD tools: VCS, Debussy, Verdi, ModelSim, Synopsys Design Compiler, Lint, Synplify, Xilinx and Altera FPGA Place and Route
Protocols: Network Protocols and PCI/PCI-Express (PCIe)
WORK EXPERIENCE
STANDARD MICROSYSTEMS CORP (SMSC), San Jose, CA 11/2007 – Present
Senior Digital ASIC/FPGA Engineer
Member of the Project Team developed three different High Speed Digital ASICs/FPGAs for Gigabit Subsystem, which handled different kind of Network Protocols including TCP/IP. These ASICs/FPGAs solution including Ethernet MAC Controller, FIFO Controller, Control and Status Register Space, DMA Controllers and PCI-Express (PCIe)/PCI/USB Modules.
• Participated with PLM Team to generate the Architecture Document for Gigabit Subsystems.
• Wrote the Micro-Architecture Documents, RTL designed and Block Level Verification the PCIe User Interface Packets, Transmit FIFO, PCI and USB DMA Controllers Modules.
• Involved with Verification Team to generate Test Cases and Debugging Chip Top Level.
• Involved with Validation Team to implement and debug the FPGA version of Gigabit Subsystems.
• ASICs/FPGAs Lab Bring-Up and Debugging.
• ASICs are fully functional and have been deployed in company products.
CISCO SYSTEMS INC, San Jose, CA 05/2002 – 08/2007
Senior Digital ASIC/FPGA Engineer
Member of the Project Team created the 10 Million gates deep sub-micron High Speed Digital ASIC 10Gbps Multi-Protocols (IP and Ethernet) Mapper for the Transport Network. A single ASIC solution including SPI-4.2 Adaptor and Controller, Memory Manager, Queue Manager, GFP/PPP Encapsulator/Decapsulator, Virtual Concatenation (VCAT) Processor, Link Capacity Adjustment Scheme (LCAS), Overhead and Pointer Processor, Backplane Interface Main and Protect, and Microprocessor Interface.
• Participated with PLM Team to generate the Architecture Document.
• Wrote the Micro-Architecture Documents, RTL designed and Block Level Verification the Memory Manager, Queue Manager and PPP/GFP Encapsulator Modules.
• Involved with Verification Team to generate Test Cases and Debugging Chip Top Level.
• ASIC Lab Bring-Up and Debugging.
• The ASIC is fully functional and has been deployed in company products.
Member of the Project Team involved in the Architecture, Micro-Architecture, Design and Debugging High Speed Digital FPGA for a Flow State Aware Router, which handled different kind of Network protocols including TCP/IP and PPP. A single FPGA solution including SPI-4.2 Adaptor and Controller, 4x3.125Gbps XAUI interfaces, XGMII Controller, DDR2 Memory Controller, Data Communication Channels (DCC) Framer Processing and PCI-Express interfaces.
• Participated with PLM Team to generate the Architecture Document.
• Wrote the Micro-Architecture Documents, RTL designed and Block Level Verification the PCIe User Interface Packets, XGMII Controllers and DCC Framer Processing Modules.
• Involved with Verification Team to generate Test Cases and Debugging Chip Top Level.
• FPGA Lab Bring-Up and Debugging.
• The FPGA is fully functional and has been deployed in company products.
FORCE10 NETWORKS/TURIN NETWORKS, San Jose, CA 04/2000 – 04/2002
Senior Digital ASIC/FPGA Engineer
Member of the team created the High Speed Digital Backplane ASIC/FPGA for a Cross-Connect switch in a Multi-Service Edge Switch which handles different kind of protocols including IP and Ethernet.
• Participated with PLM Team to generate the Architecture Document.
• Wrote the Micro-Architecture Documents, RTL designed and Block Level Verification the Block Data Processing Multi-Protocols (IP and Ethernet) Module.
• Involved with Verification Team to generate Test Cases and Debugging Chip Top Level.
• Involved with Validation Team to implement and debug the FPGA version of High Speed Digital Backplane Subsystems.
• ASIC/FPGA Lab Bring-Up and Debugging.
• The ASIC is fully functional and has been deployed in company products.
Member of the team involved in the High Speed Ingress Traffic Manager (ITM), Egress Traffic Manager (ETM) and Scheduler FPGAs for Packet Switching in a Multi-Service Edge Switch which handles different kind of protocols.
• Participated with PLM Team to generate the Architecture Documents.
• Wrote the Micro-Architecture Document, RTL designed and Block Level Verification the ITM Block Data Module.
• Involved with Verification Team to generate Test Cases and Debugging ITM Chip Top Level.
• ITM FPGA Lab Bring-Up and Debugging.
• The ITM FPGA is fully functional and has been deployed in company products.
AGERE SYSTEMS/LUCENT TECHNOLOGIES, Allentown, PA 08/1998 – 03/2000
Senior Digital ASIC Engineer
Member of the team created the 24x10/100Mbps-Port + 2xGbps-Port Ethernet Switch on a Single Chip for the Workgroup Switch. Single chip solution including Lookup Engine, Port Control, Switch Expansion Port Control, Memory Manager, Queue Manager and MAC.
• Participated with PLM Team to generate the Architecture Document.
• Wrote the Micro-Architecture Documents, RTL designed and Block Level Verification the Memory Manager and Port Control Modules.
• Involved with Verification Team to generate Test Cases and Debugging Chip Top Level.
• ASIC Lab Bring-Up and Debugging.
• The ASIC is fully functional and has been deployed in company products.
EDUCATION
Ph.D. degree in Microelectronics, Polytechnic Institute of Grenoble, France
Master degree in Microelectronics, Joseph Fourier University of Grenoble, France
Bachelor degree in Electronics, Polytechnic Institute of Grenoble, France
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