Embedded Systems

Personal Data:

Permanent Address

Mr. Arjun.B.K,

s/o Kishnakumar. B.T.,

SRKFC, Main Road, Belur Tlk.,

Hassan Dt.,

Karnataka, India.

Postal Code: 573115

Present Address

Mr. Arjun.B.K,

Hemanna Building,

Chokkasandra,Jalahalli Cross,

Bangalore

Karnataka- 573 135

Mobile : +919*********

Email

******.*****@*****.***

Personal Details

Date of Birth-28-03-1989

Sex - Male

Nationality - Indian

Languages - English, Kannada, Known Hindi, Telgu, Urdu.

Objective

To achieve excellence through continuous improvement of skills and technology and to reach best position in the field of Embedded C, Linux Internals, Device Drivers, Embedded OS, Networking and Communications.

Abstract

Well knowledged in Embedded C, Data Structures, Linux Internals, Microcontroller and Microprocessors.

Executive Summary

Experience in designing and prototyping required specifications in FPGA and Layout Design backend tools like Virtuoso from Cadence

Highly enthusiastic and persuasive with communication and Personal Relationship skills

Educational Strength

VLSI LOGIC DESIGN Training

(UTL TECHNOLOGIES LTD –Bangalore)

15th July_17th Aug 2009 - ‘A’ Grade

Bachelor of Engineering (Electronics & Communication)

2006 – 2010 -- 63.45%,

Bahubali College of Engineering, Shravanabelagola

P.U.C – S.D.M Residential College, Ujire(2006) – 61.67%

S.S.L.C – P.P.E.C High School, Belur(2004) -82.08%

Technical Expertise

1) Technical Languages : Embedded C, Data structures

2) General Technical Software : MATLAB-6 Release12,Multisim

3)Assembly Language

Technical Software

(Simulation, Synthesis,

implementation)

4) FPGA Implementation :

OS KNOWN :

SKILL SETS : : Microprocessor-8085, 8086, Mic_Controller 8051

:Virtuoso Schematic Editor, NC-Sim, Nclaunch, RTL Compiler - Cadence

Model-Sim, Xilinx - ISE 7.1- Mentor Graphics

Xilinx - ISE 9.1i- Mentor Graphics

WINDOWS XP, Vista, LINUX

Digital Electronics, VLSI, Computer Networks

Areas of Interest

• Embedded Systems

• Embedded VLSI

• Communication and Networks

ARJUN B K

EXTRA-CURRICULAR ACTIVITIES:

Technical:

1. Won second prize in 2nd National Conference on recent trends in Electronics & Communication on the topic “Security Issues in MANETs”, held in NEW HORIZON College of Engg, in association with IEEE Student branch, Bangalore

2. Participated in 2nd National Level Conference “NCOCN’10” presented and published project “Verilog Implementation of TORA Protocol for MANETs”, held in Vidya Academy of Science and Technology, Thrissur, Kerala

3. Participated in FIESTA-10,Organized by ISTE Student chapter, presented project “Verilog Implementation of TORA Protocol for MANETs”, held in Bahubali College of Engineering, Shravanabelagola, Hassan

4. Participated 1st State Level Conference on current issues in Electronics & Communication presented paper on topic “Adhoc Networks Securities” held in B.N.M.I.T College of Engineering, Bangalore

5. Presented poster on topic “Endoscopic Capsule Implemented using VLSI”, FIESTA’09 held in Bahubali College of Engineering, Shravanabelagola, Hassan

6. Attended Workshop on the topic “Practical Aspects of Broadband and Mobile Communication”, Organized by IEEE MCE Student Branch, Hassan

Hobbies:

1. Playing Basketball, volleyball and cycling

2. Watching TV, Reading books, Playing indoor games like Carom, chess

3. Listening to music, pleasant songs and Dancing

DEGREE COLLEGE:

Engineering College Bahubali College of Engineering – Shravanabelagola (Hassan)

Duration 4 years (2006 – 2010)

PROJECT DETAILS:

Company UTL Tehnologies Ltd.

Duration 1 month

Role &

Responsibility To Learn Verilog and VHDL Languages through training and create design as per customer specifications and Prototyping in FPGA and Synthesize using Cadence

Tool-sets

PROJECTS

ACADEMIC MINI-PROJECT PROFILE

1. Project Name: CAM

Client BCE

Role

Team Member

Organization UTL Tehnologies Ltd. – Bangalore

Duration 1 month (July2009)

Team Size Project: 4 Module: Front End Design

Environment

(With skill versions) Technical Software

NC-Sim, Nclaunch, RTL Compiler - Cadence

Model-Sim, Xilinx - ISE 7.1- Mentor Graphics

Project Description :

So as to access the desired memory contents and its related information and to get the specified work done CAM (Content Addressable Memory) is used. For example the ATM machines use these CAM for its working i.e. First it verifies the card number and if it is correct then it asks for the pin and if it is correct then only it gives the information about the database which is stored in his memory address, then only the user is permitted to perform the tasks which he likes, which are all stored in the data base earlier only.

Above design is prototyped using SPARTAN 3 FPGA KITS with design frequency of about 0.85GHz

ACADEMIC PROJECT PROFILE

1. Project Name: Verilog Implementation of TORA Protocol for MANETs

Client BCE

Role Team Leader

Organization BCE ,Shravanabelagola

Duration 4 months

Team Size Project: 4 Module: Front End Design

Environment

(With skill versions) Technical Software

NC-Sim, Nclaunch, RTL Compiler - Cadence

Model-Sim, Xilinx - ISE 9.1i

The most important issue to consider when designing a network system is to choose a technology which is both flexible and fast enough to support the present and future protocols and the high throughput requirements respectively. A hardware implementation of TORA protocol is performed, where the architecture of the hardware based TORA router and the method of implementation in hardware and its Simulation and Synthesis reports are obtained using Verilog. The results show that Device summery and Timing analysis, having process cycle of minimum period with 29.27 ns.

The above details is true as per my knowledge

ARJUN B K

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