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Layout, Build/Validation, QA

Location:
Oakville, ON, Canada
Posted:
June 26, 2026

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Resume:

Ninel Aghasyan

Ontario

289-***-****

*************@*****.***

-Over 15 years of experience working in semiconductor EDA environments, including Layout, Build/Validation at Synopsys and QA Engineering at Siemens

-Worked with cross-functional teams, supporting complex projects from requirements through release.

Work Experience

2022 – 2026 Siemens EDA, Canada

Software QA Engineer, Senior

Siemens Digital Industries Software

Identified, reported and verified bugs for EDA software tools

Designed and executed test plans and test cases

Performed verification for complex scenarios and documented results clearly

Verified newly developed EDA tools and features, helping eliminate issues prior to release

Worked on updating automation tests using Squish, Oblivious to improve testing coverage

Worked with developers and application engineers to support high quality and timely product releases

2012 - 2021 Synopsys, Armenia

Build/Validation Engineer, Senior II

Logic Libraries

Reviewed and analyzed project requirements and scope

Build, validation, cross-check and packaging of Logic Libraries views

Defined validation checks based on project requirements and updates

Improved build and validation flow and checks for more productivity and accuracy

Debugged issues and collaborated with cross-functional teams (Layout, IP Development, RIPD, PNR, Characterization) to resolve problems efficiently

Project leading, scheduling and final reviews

2010 - 2012 Synopsys, Armenia

Layout Design Engineer, Senior I

Analog and Mixed Signal Layout for NVM IP design

Layout projects from scratch to release

Top-level layout design

Closely worked with CAD and Schematic design teams

Project leading including schedules determination, task assignments and resource coordination

2006 - 2012 Virage Logic, Armenia

Layout Design Engineer

Layout design and physical verification of Standard Cell Libraries

Layout and physical verification for NVM IP design

Floorplanning and routing for test chips

Participated in project leadership and technical coordination

2003 - 2006 Armenian Nuclear Power Plant

System Administrator

Maintained computer systems and participated in designing network infrastructure

Provided technical support and ensured reliable operation of IT systems

Education

2003 - 2005 Master’s Degree – Electronics and Microelectronics

State Engineering University of Armenia / Approved by WES

1999 - 2003 Bachelor’s Degree – Microelectronics and Semiconductor Devices

State Engineering University of Armenia / Approved by WES

EDA tools

Cadence:Virtuoso Schematic/Layout Editor, Calibre, Laker, ICV, Custom Compiler, PrimeTime, Formality

Layout Analizer, Tanner, PVTMC Verifier, High-Sigma Monte Carlo, High Sigma Verifier, Fast PVT, Design Sense, Cell Optimizer, Worst Case Yield Solver

Operating Systems

Linux, Windows

Soft Skills

Analytical thinking and strong problem-solving ability

Attention to details and commitment to product quality

Strong teamwork and collaboration

Ability to manage multiple tasks and deliver on schedule



Contact this candidate