FPGA Engineer with Verification and Debug Expertise

Sai Jagadish

FPGA Engineer

Summary:

*+ years of hands-on experience in FPGA design, verification, and validation across networking, AI, and automotive domains, working closely with cross-functional engineering teams

Strong expertise in writing synthesizable RTL using Verilog/SystemVerilog with focus on modular, scalable, and reusable design practices

Designed and implemented UVM-based verification environments from scratch including agents, drivers, monitors, scoreboards, and sequences

Worked extensively on high-speed protocols such as PCIe Gen3/Gen4, AXI4, AXI-Stream, DDR4, and Ethernet interfaces

Experience in FPGA prototyping using Xilinx UltraScale+ and Intel Stratix platforms for pre-silicon validation

Performed static timing analysis (STA), constraint definition (XDC/SDC), and resolved setup/hold violations during timing closure

Developed reusable and configurable verification components to improve regression efficiency and reduce verification cycle time

Implemented functional coverage models and ensured coverage closure using coverage-driven verification methodologies

Debugged complex issues using waveform viewers, Vivado ILA, and SignalTap for both simulation and hardware-level validation

Designed high-throughput data paths and optimized DMA architectures for performance-critical applications

Managed multi-clock domain designs and performed CDC analysis to avoid metastability and synchronization issues

Actively involved in board bring-up, debugging hardware interfaces, and validating FPGA functionality in lab environments

Developed automation scripts using Python and TCL to support regression testing, build flows, and report generation

Hands-on experience in Embedded C/C++ for firmware interaction and low-level debugging of FPGA-based systems

Worked with microcontrollers such as STM32 and ESP32 for peripheral interfacing and control logic validation

Experience in developing firmware using FreeRTOS for real-time task scheduling and hardware control

Strong exposure to Embedded Linux environments including driver interaction, boot process, and system-level debugging

Collaborated on FPGA + firmware integration where embedded processors control FPGA data paths and peripherals

Collaborated with ASIC, firmware, and system teams for seamless integration and end-to-end validation

Experience working with FPGA prototyping platforms like HAPS for early-stage silicon validation

Hands-on experience with DDR memory interfaces including calibration, PHY configuration, and performance tuning

Debugged PCIe link initialization, LTSSM states, and throughput bottlenecks using protocol analyzers

Expertise in using synthesis and implementation tools like Vivado and Quartus for optimizing area and performance

Applied design optimization techniques such as pipelining, resource sharing, and latency reduction

Skill Matrix:

HDL & Verification

Verilog, SystemVerilog, UVM (Universal Verification Methodology), SystemVerilog Assertions (SVA)

Protocols

PCIe Gen3/Gen4, AXI4, AXI-Stream, DDR3/DDR4, Ethernet (1G/10G/100G), CAN, SPI, I2C, UART

Tool

Xilinx Vivado, Intel Quartus, ModelSim, QuestaSim, VCS, Vivado ILA, SignalTap, Synopsys HAPS

Programming

Python (automation, regression), TCL (build scripts), C (basic firmware interaction)

Debug Tools

JTAG Debugging, Oscilloscope, Logic Analyzer, CDC/RDC Analysis Tools

Process & Tools

Git, Jenkins, JIRA, Agile/Scrum

01# Project Title: High-Speed PCIe Data Acquisition System for AI Acceleration

Client: NVIDIA, USA

Duration: Jul 2025 – Present

Description: Worked on a high-performance FPGA-based data acquisition system used in AI accelerator platforms. The system handles high-bandwidth data transfer between FPGA, host CPU, and GPU using PCIe Gen4. The design includes DMA engines, AXI-based interconnects, and DDR4 memory buffering to support real-time AI workloads.

Roles & Responsibilities:

Designed RTL modules for PCIe interface including transaction layer packet (TLP) handling and AXI-Stream bridging

Developed a high-performance DMA engine supporting multiple channels for simultaneous data transfers

Developed Embedded C/C++ firmware to configure FPGA registers and control DMA operations from host side

Integrated FPGA design with Embedded Linux drivers for PCIe-based communication

Worked on bare-metal and RTOS-based firmware to validate hardware functionality during bring-up

Debugged system-level issues involving FPGA and processor interaction using JTAG and software logs

Implemented AXI4 memory-mapped interfaces to interact with DDR4 memory controllers

Created UVM-based testbench including PCIe agents, drivers, monitors, and scoreboards

Developed constrained-random test scenarios to validate edge cases such as backpressure, burst transfers, and error conditions

Implemented assertions (SVA) to check protocol compliance and data integrity

Debugged PCIe link training issues (LTSSM states) and resolved enumeration failures

Used Vivado ILA for real-time hardware debugging and signal tracing

Performed timing optimization by pipelining critical paths and refining constraints

Conducted throughput analysis and improved data transfer efficiency

Validated design on Xilinx UltraScale+ FPGA hardware platforms

Collaborated with driver/software teams for end-to-end validation of PCIe communication

Automated regression testing using Python scripts integrated with Jenkins

Participated in design and code reviews ensuring best practices and quality standards

Environment: Verilog, SystemVerilog, UVM, PCIe Gen4, AXI4, DDR4, Xilinx Vivado, Python, TCL, Git, Jenkins

02# Project Title: FPGA-Based Network Packet Processing Engine (100G Ethernet)

Client: Cisco Systems, USA

Duration: Sep 2024 – Jul 2025

Description: Worked on FPGA implementation of a high-speed packet processing engine used in networking devices supporting 100G Ethernet. The system performs packet parsing, filtering, and forwarding with strict latency requirements for data center networking applications.

Roles & Responsibilities:

Designed RTL modules for packet parsing, header extraction, and classification logic

Implemented AXI-Stream pipelines for handling continuous packet flow with minimal latency

Integrated 100G Ethernet MAC and PCS layers into FPGA design

Developed firmware modules in Embedded C/C++ to support packet configuration and control interfaces

Worked with Embedded Linux-based systems to validate FPGA networking functionality

Integrated FPGA with control-plane processors using low-level drivers and APIs

Used scripting and firmware hooks to simulate real-time network traffic scenarios

Built complete UVM verification environment for packet-level validation

Developed constrained-random traffic generators to simulate real-world network conditions

Created scoreboards and reference models to validate packet correctness

Measured latency and throughput performance and optimized data paths

Debugged packet drops and corruption issues using simulation waveforms and hardware tools

Performed CDC checks and ensured reliable data transfer across clock domains

Achieved timing closure at high frequencies (>300 MHz) through optimization techniques

Integrated FPGA with external network processors and ASIC components

Developed Python-based automation for regression and test reporting

Conducted FPGA bring-up and validated functionality in lab setup

Participated in architecture discussions and design reviews

Environment: SystemVerilog, UVM, Verilog, Xilinx Vivado, Ethernet 100G, AXI-Stream, Python, CDC Tools

03# Project Title: Automotive ECU FPGA Validation and Interface Development

Client: Bosch Engineering, India

Duration: Jan 2023 – May 2024

Description: Worked on FPGA-based validation platform for automotive ECU systems. Focused on validating communication protocols and simulating sensor/actuator interfaces under real-time automotive conditions.

Roles & Responsibilities:

Developed RTL modules for CAN, SPI, I2C, and UART communication interfaces

Created FPGA-based environment to simulate ECU signals and validate behavior

Developed firmware using Embedded C on STM32 microcontrollers for sensor and actuator interfacing

Implemented FreeRTOS-based task scheduling for real-time communication handling

Worked on ESP32-based modules for communication testing and validation setups

Performed debugging of firmware and hardware interaction issues using serial logs and debugging tools

Supported Embedded Linux-based validation setups for ECU-level integration testing

Developed testbenches for protocol-level validation and functional testing

Performed debugging of communication issues such as frame errors and timing mismatches

Used oscilloscopes and logic analyzers to validate signal integrity

Supported hardware bring-up activities and interface debugging

Validated real-time performance of communication interfaces

Automated testing using Python scripts for repetitive validation scenarios

Documented test cases, results, and validation reports for compliance

Supported EMI/EMC-related validation activities

Collaborated with embedded firmware teams for integration testing

Debugged timing synchronization issues between multiple interfaces

Environment: Verilog, ModelSim, Xilinx FPGA, CAN, SPI, I2C, UART, Python, Oscilloscope

Education:

Masters in Electrical and Electronics Engineering, California State University, Sacramento, CA 2026

Bachelor of Technology (B.Tech) in Electronics and Communication Engineering (ECE), India

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