Senior Hardware Test Engineer and Validation Lead

Ty Xuan Do

***** ***** ****, ***** ****, CA ***** Phone: 510-***-**** Email: *******@*****.***

Objective: Hardware Test Validation Engineer or a Technical position.

Knowledge Experience Expertise

-Expert in PCBA testing, debugging, analyzing with DVM, oscilloscope, logic analyzers, signal generator and voltmeter.

-Extensive experience with high-bandwidth oscilloscopes, BERTs and associated lab equipment for SERDES characterization.

-Experience on High and Super Speed signal measurement equipment for testing, debugging such as LeCroy High speed Signal Analyzer SDA 813Zi-B 16GHz 4x40GS/s, PeRT3 Eagle (BERT) and Keysight J-Bert M8020A

-Experience in USB1/2/3, SATA SSD/HDD, HDMI, MIPI compliance testing procedure and eye diagrams measurement by using LeCroy High speed Signal Analyzer and Keysight Digital Signal Analyzer high speed oscilloscope 13Ghz DSAV134A and 33Ghz UXR0334A.

-Experience in transceiver/SERDES validation and characterization, S-Parameter TDT/TDR (Time Domain Transmission (S21 Time Domain Reflectometry S11) high speed signal integrity circuit validation and power integrity.

-Knowledge of PCIe and DDR highspeed interface validation.

-Experience in Post-Silicon validation and Corner lots thermal test.

-Knowledge of various Bus interfaces including SPI, I2C, UART, USB2/3, USBC, MIPI, etc.

-Experience with interconnects: USB, HDMI, Display port, MIPI

-Experience in lab experimental tools: VNA (ENA-E5080 and PNA-N5222A), TDR, BERT, Real-Time/Sampling Scopes, High speed.

-Knowledge of signal integrity concepts such as S-parameter, insertion loss, reflections, cross talk, etc.

-EDA/CAD tools: AutoCAD, Cadence OrCAD and Allegro 16.6, PADS Logic and PADS PCB Layout 9.3

-Operating Systems: MS-Windows 7/8/10, gLinux, Android OS and ADB Command.

-BASIC knowledge Programming Languages: C, Python, Shell Scripting.

-Software Tools: Agile BOM management, Reliability Analysis & Safety Software Tool (MTBF) ItemSoft, MS-Excel/Word/Visio.

Works experience responsibility

Meta, Sunnyvale CA 12/15/2024- Present

Prototype Electrical Test Engineer (Contingent)

-Perform System Level Test (SLT) for all Meta Head Set product.

-Support prototype design, builds, validate and test which include AR/VR headset, MLB, PCBA.

-Perform system and board bring-up for all AR/VR new design products.

-Perform failure analysis, root cause and preventive and corrective actions.

-Collaborate in a team environment with cross-functional teams such system engineering, architecture, product design, NPI.

Nvidia, Santa Clara CA 5/13/2024 – 12/15/2024

Sr. Post Silicon Validation Engineer – HSIO (Contract)

-Participated in Nvidia Tegra SOC Post Silicon Validation for USF, HDMI, USBc

-Working closely with Architecture and Design teams include defining validation plans, bring up, debug SOC issues and coordinating to run tests.

-Perform the signal integrity validation for High and Low Speed I/O interfaces such UFS, USBc, HDMI.

-Setup and perform the thermal for SOC test.

-Supporting software engineer to develop the test software to validate high speed I/O.

-Extensive experience using Max-TC High Power Temperature forcing system for testing the SOC.

-Used high speed Keysight Oscilloscope and J-Bert M8020A High Performance Bert for high speed I/O signal validation.

Google, Mountain View CA 5/22/2023 – 5/8/2024

Hardware Validation Engineer (Contract)

-Perform Electrical power and I/O signal Validation for Fitbit/Pixel watch Products including MCU, RF/WiFi and MLB Base boards.

-Work experience with gLinux and ADB command for troubleshoot, debug and failure analysis of google watch.

-Test and validate the various voltage rails, low-speed signal interface I/O signals I2C & SPI, high-speed differential interface, electrical performance of subsystems such as battery, charger, various watch sensors, USBc, display interface, etc.

-Work with the design team to debug problems and performance issues.

-Execute special test requests from the design team to measure specific parameters or root cause issues.

-Participate in engineering reviews including schematic, layout with both cross-functional teams and engineering teams.

-Implement test plans to test and validate changes and ensure product reliability.

-Support in high speed test signal integrity including VNA TDT/TDR, Eye Diagram measurement, S-Parameter measurement.

Apple, Cupertino CA 8/8/2022 – 5/15/2023

Electrical Engineer - Hardware Test & validation (Contract)

-Perform FATP-SoC Testing and Validation for various new developed laptop computers and SoC test systems with various bundles released software and overlay software revision.

-Perform software and hardware regression testing for various SoC test systems.

-Perform Electrical/Hardware validation, signal probing and debugging by using Oscilloscope.

-Validation coverage includes low-speed signal interface I/O signals, high-speed differential interface, electrical performance of subsystems such as microphones, cameras, battery and charger, etc.

-Report of system test, electrical validation work status and clearly document test results.

-Support systems bring up and debug activities and Keep track of bugs encountered and fixed.

Meta (Facebook), Sunnyvale CA 7/12/2021- 7/11/2022

Hardware Test Engineer (Contingent)

-Responsible for Meta Portal video product hardware testing.

-Performed Power Delivery compliance testing for Meta Portal video product hardware with Granite River Lab (GRL) equipment.

-Performed the power rail consumption test for various voltage at various temperatures by using PXI National Instrument for data acquisition and created the report.

-Performed USB, HDMI and MIPI compliance testing.

-Performed the high speed test signal integrity including VNA/TDT/TDR for Portal video hardware circuit board, signals measurements, and high speed signals eye diagram measurements.

-Validated low speed bus protocol validation for I2C, SPI, etc.

-Worked with team engineers to provide timely and meaningful results driven by product release schedule.

-Created Unit Test cases, analyzing and designing automation requirements for hardware testing.

-Created and developed QA test plans and implemented automated testing scripts for various hardware test projects.

-Software/hardware bug regression planning and implementation.

-Support in high speed test signal integrity including VNA (Keysight ENA-E5080)/TDT/TDR.

Microsoft, Mountain View CA 9/1/2018- 7/11/2021

Lab Engineer (Contract)

-Performed the calibration and quality test for Image and Illuminate modules. Test including Electrical test, Focus test, Optical, registration test, etc by using Robotic, Matlab and Python scripts automation.

-Performed test and debug the MLB and interposer boards and camera.

-Performed Camera calibration and characterization test including image and illuminate module. Tests including dynamic range test, intrinsic image test, flat (gray color) wall tests, etc. by using Matlab scripts automation.

-Performed the reliability test Halt and Hass thermal testing system and collected data for failure analysis, environmental chamber testing, temperature characterization and thermal imaging testing for depth sensor and camera.

Cisco, San Jose CA 4/6/2018 – 8/30/2018

FA Engineer (Contract)

-Performed failure analysis on Cisco Nexus 7K/9K families systems including power supply, switches and routers.

-Performed the QA python test automation software for analyzing the system and component failure.

-Conducted root causes analysis of defective electronic components from system to component level, identify problems and make corrective action and ensure corrective actions are implemented.

-Implemented methodologies for collecting and analyzing field failure data and determining root cause of field failures.

Microsoft, Mountain View CA 8/30/2016- 3/30/2018

Lab Engineer (Contract)

-Executed validation test plans for X-Box CPU and GPU to ensuring they meet performance, reliability, and compliance standards.

-Performed power, thermal, and stress testing, as well as functional validation across different hardware configurations.

-Debugged and analyzed hardware failures, working with cross-functional teams to identify root causes and drive resolutions.

-Use lab equipment oscilloscopes, logic analyzers, etc. to troubleshoot issues and validate signals.

Initio Corporation, San Jose CA 5/2010 – 7/31/2016

Sr. Hardware Test Engineer (Post silicon IC validation)

-Support Pre-silicon and post-silicon validation for the USB-Sata Bridge new chip including hardware test, validation, and bring up.

-Supported reference test board designs, debugging and bringing up prototype boards for USB1/2/3 to SATA SSD/HDD.

-Perform Post Silicon Validated and characterized new Sata-USB1/2/3 bridge chip and USB Type C interface across DVT and PVT.

-Performed reliability test Halt and Hass thermal testing system and collected data for failure analysis for the new Silicon USB2/3 - SATA bridge IC.

-Performed USB1/2/3, SATA HDD/SSD test validation, compliance testing, high speed signals and eye diagrams measurement and verification, and compatibility testing with various operating systems and analyzed test results and identify potential issues, debug and root cause to produce optimal USB 1/2/3 transceiver performance.

-Created test plan/procedure for compliance testing and characterization of the USB2/3, SATA HDD/SSD device.

-Provided detailed coordination between hardware and software teams for bug fix, corrective action and implementation.

-Debugged and analyzed defective USB-SATA ICs that were returned by customers.

-Validating and characterizing the performance transceiver (SERDES) for SATA-HDD to USB1/2/3 bridge IC.

-Assisted the migration of reference designs to production.

Deeya Energy, Fremont CA 6/2009 – 4/2010

Electronic Layout Engineer

-Performed Pads Logic Schematic Capture, Pads PCB layout for analog, digital, and mix signal for power supply circuit boards including buck-boost, Embedded CPU controller, patch panel, electrolyzer, sensors, and Mixed-signal circuit boards.

-Performed Board prototype bring up, debug and design verification testing.

RGB Spectrum, Alameda CA 11/2004 –5/2009

Component Engineer

-Evaluated new part selections during research, concept development and new product development to identify supply chain issues and risks (EOL, Long Lead time, RoHS/REACH, etc...).

-Managed NPI introduction process and production documentation management to include: BOM/AVL creation, review and validation.

-Created documentation such as ECO/ECN creation and coordination documentation and general process

-Developed, implemented, and maintained test process instructions (TPI) for production.

Runco International (Home Theater), Union City CA 4/2001- 10/2004

Test Engineer

-Defied video test protocol and developed the test plans for evaluation video displays and controllers.

-Developed and executed test protocols to provide unit, coverage, and testing throughout the software development cycle.

National Display System, Morgan Hill CA 11/1996 - 4/2001

Electrical Engineer

-Board level design, debug, bring up, testing RGB A/D video controller, video interfacing, audio amplifier by using Orcad, Pads Logic Schematic Capture and Pads PCB layout.

Dolch Computer Systems, Fremont CA 7/1991 – 11/1996

System Engineer

-Developing the new portable computer, Flat Panel Monitor.

Education:

Bachelor of Science Degree in Electrical Engineering (BSEE), California State University of Fresno Department of Electrical and Computer Engineering, CA, May 1991

Cisco Certified Network Certificate-Association (CCNA), Ohlone College, Fremont, CA, 2010

Emphasis in Cisco network router and switch, TCP/IP, Ethernet, Wi-Fi, network design and configuration.

Certificate of Professional PCB Design, Copper Connection Inc., Santa Clara, CA 1996

Certificate of Industrial Electronics, Woodruff Occupational Center, Stockton, CA 1986

Citizenship: U.S. Citizenship.

References: Available upon request

Linkedin: https://www.linkedin.com/in/ty-do-5a354b215/

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