Edge AI & Computer Vision Engineer Lead

VO QUOC DAT

Computer Vision Engineer & Edge AI Engineer

+ Ho Chi Minh City 093*-***-*** # *********@*****.*** ï in/dat614943 § github.com/dat2003as PROFESSIONAL SUMMARY

AI Team Lead and Edge AI Engineer specializing in architecting commercial-grade computer vision pipelines and migrating restrictive architectures to license-free solutions (RTMDet, PPYOLOE-R). Proven expertise in deploying server-side vision modules for real-world constraints, while actively driving R&D initiatives to compile highly optimized execution graphs (.engine, .cix) for edge hardware (NVIDIA Jetson Nano, Orange Pi 6 Plus).

TECHNICAL SKILLS

Hardware & Edge AI NVIDIA Jetson Nano, Orange Pi 6 Plus (CIX 45 TOPS), TensorRT (.engine), ONNX .cix, Hardware-aware Optimization.

Deep Learning Stack PyTorch, PPYOLOE-R, RTMDet, YOLOX, EfficientNet, timm, Metric Learning, ONNX Runtime, CBAM Attention. Languages & Tools GStreamer, OpenCV, Python, Shell Scripting, Embedded Linux, Docker, ZeroMQ, FastAPI. Generative AI RAG Architectures, LangChain, Qdrant (Vector DB), Local LLM Integration (Llama 3.2). PROFESSIONAL EXPERIENCE

AI Team Lead Nov 2025 – Present

Mebisoft Ho Chi Minh City

• Spearheaded a server-side aquaculture vision pipeline, strategizing themigrationfromrestrictiveYOLOmodelstoApache2.0/license- free architectures (RTMDet, PPYOLOE-R, YOLOX) for commercial deployment.

• Engineered a high-density object counting module (1024x1024 input) by orchestrating cross-functional mobile UI constraints for fixed-aspect ratio cropping, boosting real-world accuracy to 90% for sparse and >80% for highly overlapped environments.

• Formulated a production-ready measurement system fusing RTMDet-Seg with ArUco-based skeletal geometry, achieving a strict

<10% measurement error against physical benchmarks in real-world operations.

• Engineered a hardware-aware compilation pipeline for high-density aquaculture counting, translating PPYOLOE-medium into opti- mized TensorRT (.engine) graphs. Validated architecture scalability by securing a >120 FPS baseline on RTX 3050Ti to derisk through- put constraints prior to physical Jetson Nano deployment.

• Developed a Proof-of-Concept (PoC) anomaly detection pipeline using sequential segmentation and EfficientNet-B0 with CBAM attention, securing 94% accuracy on test sets (production deployment pending long-term farm data collection). Edge AI Engineer May 2025 – Oct 2025

Be-Earning § Repo Ho Chi Minh City

• Accelerated inference throughput by 3 vs. CPU baseline by engineering a custom ONNX-to-.cix model compilation pipeline tar- geting the 45 TOPS CIX CD8180 NPU.

• Engineered a low-latency video ingestion pipeline via GStreamer and adaptive frame skipping, decoupling capture from AI inference. Reduced input lag to <50ms, ensuring smooth tracking at 5–7 FPS on embedded constraints.

• Optimized multi-task biometric models (PyTorch Lightning) using MixUp and class-weighting to mitigate data imbalance, securing

>85% validation accuracy under strict edge memory constraints.

• Implemented Adaptive Recognition Logic fusing CCCD, Face ID, and Body Re-ID vectors via multi-index FAISS retrieval, achieving

<1.5s latency for billion-scale database matches.

NOTABLE PROJECTS

Enterprise RAG Microservices System § Repo Runner-up, NTTU AI Comp. 2025

• Designed a scalable RAG microservices architecture handling concurrent requests via Kafka and Docker Compose; integrated Llama 3.2 and Qdrant Vector DB.

Ultra-Low Latency Gesture Control § Repo Innovation Award, NTTU AI Comp. 2024

• Built a real-time HCI system (<50ms latency) by optimizing serial communication between a Python CV pipeline and Arduino micro- controllers.

EDUCATION

Bachelor of Information Technology 2021 – 2025

Nguyen Tat Thanh University GPA: 3.47/4.0

Contact this candidate