Aspiring FPGA Engineer VHDL & RTL Design

Ansh Patel

757-***-**** ● ***********@*****.*** ● www.linkedin.com/in/apatel0402

Objective

Computer Engineering senior seeking an entry-level Digital Hardware / FPGA Engineer role focused on VHDL, synchronous digital design, and RTL verification.

Education

Virginia Commonwealth University, Richmond, VA Expected Graduation: May 2026 Bachelor of Science in Computer Engineering

Minors: Computer Science, Artificial Intelligence

Technical Skills

HDLs: VHDL

Digital Design: synchronous design, pipelining, finite state machines (FSMs), RTL design, Datapath/control separation Computer Architecture: 5-stage pipelines, hazard detection, forwarding, stall control Verification: testbench development, functional simulation, timing validation, debugging FPGA / Tools: Vivado, RTL simulation, FPGA synthesis and implementation, modular hardware design Relevant Experience

Teaching Assistant, VCU College of Engineering, Richmond, Virginia August 2025 – Current

• Assisted instruction for undergraduate engineering labs, reinforcing complex technical concepts through guided problem-solving

• Lead weekly office hours and review sessions, providing one-on-one and group support that improved student comprehension and performance.

• Graded assignments, lab reports, and exams for a class of ~70 students, ensuring timely, consistent, and constructive feedback.

• Supported hands-on experiments and software use (e.g., MATLAB, CAD, circuit analysis tools) by troubleshooting technical issues during lab sessions.

• Collaborated with faculty to develop course materials and exam questions, aligning assessments with course learning objectives.

Relevant Projects

Fully Pipelined CPU with Hazard Detection and Full Forwarding Unit – VHDL Fall 2025

• Designed and Implemented a 16-bit, five stage pipelined CPU (IF, ID, EX, MEM, WB) in VHDL using modular RTL design

• Developed hazard detection and forwarding logic to preserve correct program execution during data and control hazards

• Integrated pipeline registers between stages to enable continuous instruction flow and improve pipeline throughput

• Implemented core components including ALU, register file, control unit, and instruction/data memory interfaces

• Verified full program execution using comprehensive VHDL testbench and Vivado simulation to validate functional correctness and pipeline behavior

3-Axis Accelerometer Interface (ADXL345) – VHDL/FPGA Fall 2025

• Designed a hierarchical VHDL-based FPGA system to interface with an ADXL345 3-axis accelerometer using the SPI protocol

• Developed a synchronous finite state machine (FSM) to sequence SPI read/write transactions for device configuration and data acquisition

• Implemented signed 16-bit acceleration data handling for X, Y, and Z axes using two’s complement representation

• Designed binary-to-BCD conversion logic and time-multiplexed 7-segment display control to present real-time sensor data

• Verified correct operation through RTL simulation and modular testing, ensuring accurate SPI timing, data integrity, and synthesizable design

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