RTL Design Engineer

ROHIT KUMAR SINGH

RTL Design Engineer *.* Years Experience in FPGA Design, VerificaƟon & High-Speed Ethernet Systems Email id: **********@*****.*** Contact No.: +91-755******* LinkedIn: www.linkedin.com/in/rohit-singh-r4232 Current Loc.: Noida, India PROFESSIONAL SUMMARY:

Results-driven RTL Design Engineer with 4.5+ years of experience in FPGA design and verificaƟon using Xilinx and Siemens EDA tools.

Proficient in Verilog/VHDL for RTL development of complex digital designs and mulƟ-clock domain systems.

Experienced in Xilinx Vivado and QuestaSim for design, simulaƟon, and debugging.

Hands-on experience with Xilinx Zynq-7000 and Zynq UltraScale+MPSoC devices.

Strong understanding of digital design fundamentals, SoC architecture, and integraƟon concepts.

ExperƟse in RTL coding, Ɵming closure, linƟng, synthesis support, and FPGA debugging using ILA.

Familiar with ASIC and FPGA design methodologies, including CDC and STA concepts.

Comprehensive understanding of AXI, I2C, SPI, UART, and Ethernet protocols.

Experience with high-speed interfaces including Gigabit Ethernet, HDMI, and GTX transceivers.

Skilled in debugging complex hardware issues and opƟmizing RTL for performance and resource uƟlizaƟon.

Familiar with scripƟng in Python and TCL for design automaƟon and debugging support.

Strong team player with a proacƟve learning aƫtude and commitment to standard coding pracƟces. TECHNICAL SKILLS:

HDL Languages: Verilog, VHDL, SystemVerilog (Basic)

FPGA Tools: Vivado, ISE, QuestaSim, ModelSim

Protocols: AXI, Ethernet, UART, SPI, I2C, HDMI

FPGA Plaƞorms: ArƟx-7, Zynq-7000, Zynq UltraScale+

VerificaƟon: CDC, LinƟng, SimulaƟon, Debugging

Timing: STA, Timing Closure, Constraints

ScripƟng: TCL, Python

Debug Tools: ILA, Vivado Debugger

EXPERIENCE:

Aujus Technology Pvt. Ltd. - Senior FPGA / RTL Design Engineer DuraƟon: October 2021 – Present

Domain: RTL Design, FPGA Development, SoC IntegraƟon, and VerificaƟon Tools & Technologies: Xilinx Vivado, ModelSim/QuestaSim, TCL, Python, ILA, Oscilloscope.

Worked on architecture-level design and development of FPGA/SoC-based digital systems for high- speed communicaƟon and signal processing applicaƟons.

Designed and developed RTL code using Verilog/VHDL for complex digital blocks and mulƟ-clock domain systems on Xilinx FPGA plaƞorms.

Performed simulaƟon-level tesƟng and funcƟonal verificaƟon using ModelSim/QuestaSim by developing module-level and system-level testbenches.

Designed FSM-based control logic and reset synchronizaƟon circuitry for mulƟ-clock domain systems.

Created and managed XDC Ɵming constraints for clocking, I/O, and mulƟ-clock domain FPGA designs.

Conducted Clock Domain Crossing (CDC) checks, linƟng analysis, and StaƟc Timing Analysis (STA) to ensure reliable and Ɵming-clean designs.

Supported synthesis, implementaƟon, Ɵming closure, and opƟmizaƟon acƟviƟes using Xilinx Vivado tools.

Worked on SoC-level design integraƟon involving AXI4/AXI-Lite, Ethernet, HDMI, SPI, I2C, UART, BRAM, FIFO, and Xilinx IP cores.

Developed and integrated high-speed Ethernet interfaces including 1G Ethernet and GTX-based communicaƟon systems.

Generated FPGA bitstream files and performed FPGA programming and hardware validaƟon on ArƟx- 7, Zynq-7000, and Zynq UltraScale+ MPSoC plaƞorms.

Performed board-level debugging and hardware validaƟon using Integrated Logic Analyzer (ILA) and Oscilloscope for signal analysis and issue resoluƟon.

Worked closely with cross-funcƟonal teams including verificaƟon, embedded soŌware, and hardware teams for system integraƟon and debugging support.

Automated Vivado design flow processes including synthesis, implementaƟon, and bitstream generaƟon using TCL scripƟng.

Contributed to projects involving Ethernet Switch, IRIG-B Ɵming systems, HDMI video processing, and FFT-based signal processing applicaƟons.

INTERNSHIP/TRAINING:

PinE Training Academy — FPGA System Design Trainee DuraƟon: April 2021 – September 2021

Domain: FPGA Design, RTL Development, and SimulaƟon Tools & Technologies: Xilinx Vivado, ISE, ModelSim, Verilog, VHDL

• Learned FPGA design flow including RTL design, simulaƟon, synthesis, implementaƟon, and bitstream generaƟon using Xilinx tools.

• Developed and simulated RTL modules using Verilog/VHDL for digital design and signal processing applicaƟons on Xilinx Zynq-7000 plaƞorms.

• Gained hands-on experience in architecture-level understanding of FPGA-based embedded systems and SoC plaƞorms.

• Performed funcƟonal simulaƟon and module-level tesƟng using ModelSim to verify RTL funcƟonality.

• Worked on Ɵming analysis, basic CDC concepts, synthesis flow, and FPGA implementaƟon methodologies.

• Integrated communicaƟon interfaces such as UART, SPI, and GPIO with FPGA designs for embedded applicaƟons.

• Performed FPGA hardware validaƟon and debugging using ILA and onboard debugging tools.

• Learned Linux-based embedded development flow and basic DSP algorithm implementaƟon on FPGA plaƞorms.

• Collaborated with mentors and team members to understand industry-standard RTL coding pracƟces and FPGA development methodologies.

PROJECTS UNDERTAKEN:

Industrial Project:

1. Ethernet Switch 1G

Technology: Xilinx Vivado Verilog/VHDL FPGA: ArƟx-7

DescripƟon: Designed and implemented an 8-port 1G Ethernet Switch on ArƟx-7 FPGA using VHDL, integraƟng Tri-Mode Ethernet MAC (TMAC) and PCS/PMA IP for high-speed Gigabit communicaƟon. Developed pipelined packet processing, MAC-based switching, BRAM-based buffering, and mulƟ-clock domain handling with CDC synchronizaƟon, achieving reliable line-rate performance and Ɵming closure at 125 MHz

2. Timing DisseminaƟon Control Unit

Technology: Xilinx Vivado Verilog/VHDL Board: Zedboard

DescripƟon: Developed a real-Ɵme countdown and Ɵming disseminaƟon system on the ZedBoard using Verilog/VHDL and Vivado for vehicle launch Ɵming applicaƟons. Implemented IRIG-B Ɵme synchronizaƟon, countdown Ɵmer (CDT) control through hardware and GUI, and Ethernet-based Ɵme disseminaƟon to a server along with interfacing for Seven Segment Display, OLED, and RS232. 3. VD Hold Interface Unit (VD-HIU)

Technology: Xilinx Vivado Verilog/VHDL Board: Zedboard

DescripƟon: Designed a remote HOLD UNIT to halt countdown Ɵming in auto-launch missile systems. The unit connects to the base staƟon server for synchronized operaƟons. 4. Time Stamp and Video Mixing Over High-DefiniƟon Video.

Technology: Xilinx Vivado Verilog/VHDL Board: ZYNQ UltraScale+ MPSoC ZCU106

DescripƟon: Designed and implemented a real-Ɵme FPGA-based video processing system on the ZCU106 EvaluaƟon Board using Verilog/VHDL and Xilinx Vivado to overlay Ethernet-received Ɵmestamp data onto live HDMI camera video streams. The design supported resoluƟons up to 4K60p with configurable Ɵmestamp posiƟon, size, and color using pixel-level video mixing and font rendering techniques. Performed simulaƟon, Ɵming opƟmizaƟon, and hardware validaƟon using ILA and HDMI display tesƟng. 5. Fourier Transform Infrared Spectroscopy (FT-IR).

Technology: Xilinx Vivado Verilog/VHDL Board: ZYBO Z20

DescripƟon: Designed and implemented an FPGA-based signal processing system for FT-IR applicaƟons on the ZYBO Z20 using Verilog/VHDL and Xilinx Vivado. Implemented high-speed FFT processing for analog signal analysis where ADC samples were captured at 200 kHz, buffered into BRAM, and transmiƩed at 125 MHz for further spectral processing. The design included ADC interfacing, BRAM- based frame buffering, clock domain crossing, FFT integraƟon, and high-speed data streaming with opƟmized Ɵming and resource uƟlizaƟon.

ACADEMICS:

Professional QualificaƟon

B.Tech (2016-2020) in Electronics & CommunicaƟon Engineering from Dr. A.P.J. Abdul Kalam Technical University, UƩar Pradesh with an overall 7.4 CGPA. ADDITIONAL INFORMATION:

Open to relocaƟon for beƩer career opportuniƟes.

AcƟvely learning advanced FPGA design and verificaƟon methodologies.

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