Electrical & Computer Engineering-VLSI & ASIC Specialist

RAKESHRAM MAGESH

602-***-**** • *****************@*****.*** • linkedin.com/in/rakesh-ram-magesh-7a32791a6 • Citizen of USA SUMMARY

Electrical and Computer Engineering graduate student at ASU with end-to-end experience from custom cell layout and parasitic extraction to RTL synthesis and place and route using Cadence Virtuoso, Innovus, and Calibre on 7nm FinFET technology. EDUCATION

M.S., Computer Engineering: Specialization: Electrical Engineering August 2025 – May 2027 Arizona State University, Tempe, AZ 3.4 GPA (current) B.Tech., Electronics and Communication Engineering September 2021 – July 2025 Vellore Institute of Technology, Chennai, IND

Relevant Coursework: Digital Systems Design, VLSI System Design, Computer Communications and Networks WORK EXPERIENCE

Data Entry Operator (Part-Time) February 2026 – April 2026 Jeffrey J. Quatrone PLLC, Phoenix, AZ

• Performed efficient data entry of client tax information including 1099 and W-2 forms using Drake Tax Software

• Organized and maintained digital records for individual and business tax filings

• Reviewed and verified source documents for completeness and accuracy prior to data entry TECHNICAL SKILLS AND CERTIFICATIONS

Simulation Tools: Cadence Virtuoso, Cadence Innovus, HSPICE, LTSpice, MATLAB, AutoCAD Programming and HDL: Embedded C, Python, Verilog

Automation Tools: Automation Anywhere Software, Drake Tax Software Certifications: Automation Anywhere Certified Essentials RPA Professional – August 2023 PROJECTS

2-Bit Adder – Full ASIC Flow (Synthesis + APR) March 2026

• Synthesized RTL Verilog using Synopsys Design Compiler with ASAP7 7nm PDK, mapping to standard cells and verified functionality in ModelSim pre- and post-synthesis

• Performed full APR in Cadence Innovus including floorplanning, placement, CTS, and routing

• Achieved clean DRC verification

• Exported GDS and streamed into Cadence Virtuoso for LVS verification, completing the full RTL-to-GDS flow Design of NAND2xp5 Cell with 7nm FinFET Tech March 2026

• Designed the NAND2xp5 standard cell using the ASAP7 PDK for 7nm FinFET technology and developed the layout with all relevant linear interconnects

• Verified DRC and LVS using Calibre on Cadence Virtuoso and performed parasitic extraction to evaluate pre and post layout delays along with key performance metrics

D Flip Flop Design and Layout Verification December 2025

• Characterized NMOS and PMOS devices using Ids–Vds and Ids–Vgs simulations

• Designed CMOS inverter and NAND gate with VTC and propagation delay analysis

• Implemented custom layouts and achieved DRC and LVS clean verification PROFESSIONAL DEVELOPMENT & CERTIFICATIONS

• Automation Anywhere Certified Essentials RPA Professional (August 2023)

• Completed advanced technical workshops: Machine Learning, Deep Learning, Fine-Tuning Large Language Models, Computer Vision Fundamentals

• Participated in Intel’s “Unleash the Power of Mini Computing: Pi-thon 2023” competition, demonstrating commitment to continuous learning

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