Field Service Engineer Global Instrument Support & Diagnostics
Resume:
WILLIAM F. HUNSICKER
New Tripoli, PA 18066
**********@*****.***
Work Experience:
Lab-machines Inc.
**** ********* ****, *********, ** 18073 12/2022– 11/2024
Laid off 11/2024
East Alanttic and Europe Field Support of Acoustic Dispense Equipment
Maintenance and Repair for contract and T&M customers
Beckman LS/Labcyte Inc.
1190 Borregas Ave., Sunnyvale, CA 94089 7/2008 – 10/2022
Field Service Engineer
Cradle to grave Service of E5XX ADE (acoustic drop ejection) machine dispensing 2,5 nL drops
Feedback to R&D customer software/hardware issues – Salesforce.com data entry – tracking
Respond to customer requests and support team FAE
Support Lemonade software/hardware roll out across World
Field Service of Echo ADE Instrument. Proficient in system debug/service including RF section, auxiliary sensors and detectors, stepping motors, fluidics, pneumatic and mechanical system(s)
Field Service of Pod/Access integrated robotic High Throughput Screening System
Database backup and repair of SQL database for onsite customer systems
Linux Scripting and stress test development for picotool domain (bash script)
Support Repair, Maintenance and Echo 5xx instruments – repair hardware and address software issues
Performed Installations and upgrades of Hardware and Software
Install and License Applications software
Performed Customer Training
Customers: Pharmaceutical industry. Customer sites visited: Europe, North America and Asia
RF Micro Devices
7628 Thorndike Road, Greensboro, NC 27409 12/04 – 6/2008
Validation Lead for Digital Cellular Product Line – Staff Engineer
Test Time Reduction Lead – Development of PXI based system to increase throughput and accuracy
TX Test - Implemented Aeroflex ADC to replace R&S CMU 200 - Reduced cost by 70% and decreased test time by one order of magnitude. Developed MOD/SWITCH ORFS TEST and EVM TEST. TX Spurious Search on Tektronix Real Time Spectrum Analyzer
Identified/Resolved gold Stud Bump assembly issue and instituted screen and direct/verified fix
RX – Test - Implemented NI 5922 ADC to replace Spectrum Analyzer – 60% Cost reduction and factor of 5 test time reduction. GAIN/CN/COMPRESSION TESTS. Developed adaptive search method to reduce test time test time by 50%. Improved Out Of Band Blocker test methods/hardware for 70% test time reduction from DC to 12.5 GHz
Wrote Awk/Shell/Cron/Jump script to collect and compile compliance Matrix (ATE and Lab)
XTAL Oscillator Parallel test rack development – Reduce rack cost 60% and decrease test time by one order of Magnitude. Developed R software to analyze tuning curves over PVT
Wrote R script to analyze 30M data point tuning curve file
Verification of GMSK/8-PSK Cellular Transceiver (.85 – 1.9 GHz @ 1W)
Customer support of Transceiver Form Factor Board Development – Spectre analysis of touchstone extraction
Designed Membrane core for wafer probe of transceiver (Cascade Core and Manual Prober) – Spectre Analysis
Identified equipment set for Polaris 3 Verification
Wrote Java XML generator for Spec Entry of Nokia and Motorola Transceiver
Verification plan for Polaris 3 chip set
Designed low phase noise Clock Buffer Driver for ATE RX test Rack
Wrote Visual Basic 6 code for GPIB control of Automated Test Rack
Support Lab Test, Calibration /Maintenance Schedule working with Agilent Calibration & Technician
Develop and Maintain Package handler Software/Hardware for validation and merge ATE/lab data
Agere Systems Allentown, PA
1110 American Parkway NE, Allentown, PA 18109 10/01– 11/04
Design Engineer for Mass Storage and Analog Org. - MTS
Design of 4.25 GB/s sATA interface. Verification of digital functionality, compliance to sATA standard and characterization using standard digital and RF measurement techniques. Circuit sections include VCO, band gap, BOWR output buffer and minor digital section to repair clock domain error.
Schematic Capture (composer), circuit simulation (Spectre) and verication (caliber) of Serial Interface
Implemented design changes to improve yield and reliability of sATA die.
Design, verify and validate low power version of VCO. Take existing design of interface and take measures to reduce power, reduce jitter and physical area for laptop application.
Design and verification of 3rd overtone crystal oscillator
Return Loss and TDR analysis of sATA interface using Spectre and in Lab – Analysis of touchstone extraction
Support customer requests and developed transistorless models of I/O for customer evaluation of sATA and BOWR interface
Design Ultra640 SCSI Buffer – Design, verify and validate the Ultra 640 SCSI buffer, a mixed signal, 5 volt tolerant, 3.3V/1.5V operational buffer. 3.125ns period buffer capable of LVD/SE, programmable output Celerity/Spectre/Hspice verification – Pre/post extractions
offset, rise times and amplitudes. Validated design against Customer specification verified (LVS) and documented..
Support of Maxtor and Seagate SOC development and RFQ
Evaluation board design/support for 4.25 Gb/s sATA interface and crystal oscillator design.
Debug of ST Micro embedded 0.13 micron SRAM.
Yield Improvement and Test Development of Etron 2MX8 and 8MX8 DRAM MCP.
In-Chip Systems, Inc
Cedar Crest Boulevard, Allentown, PA 18103 (Closed) 01/01 – 06/01
Installed and Connect TCP/IP network (10/100 lan)
Configured router CSU/DSU, Red Creek Ravlin (VPN) to seam with In-Chip Network and Sun enterprise file server
Digital Design and Verification of 140 standard cells
Evaluated layout, power routing and utilization of customer’s logic library
Branch office closed due to business constraints on 5/24/01
Agere Systems/Lucent/AT&T Bell Laboratories Allentown, PA
555 Union Boulevard, Allentown, PA 18103 08/80 – 12/00
Circuit Design - Design Engineer for Mass Storage and Analog Org. - MTS
Wrote Shell/C/tcl/awk and S scripts for flow development of post place and route CAD
Developed MATLAB script for Hspice post processing.
Worked with circuit design of SCSI buffer—added de-skew circuitry
All aspects of SCSI I/O design digital and analog components, including Composer schematic capture, Spectre and Hspice Simulation, Ocean Script development for iterative analysis of SCSI buffer.
Optimized OP-amps for decreased power consumption
Evaluated simulated and laboratory signal integrity issues with customer
Worked with customer on the development of HSPICE and IBIS model
Worked with chip-level verification tools (Goalie and Gemini) on the Redwood design
Engineer - Yield Enhancement Systems - MOS V Engineering (MTS-I)
Wrote C/Awk/Shell software to correlate data from in-process inspection to probe data
Related myriad of databases from KLA & Tencor inspection tools at various process steps to electrical test bitmaps from wafer probe
Performed statistical analysis and mapping to determine critical fabrication steps
Supported and enhanced electrical bitmap analysis for various DSP codes such as 1616, 1620 and 1632 on the Advantest and Credence platform for yield improvement
Microelectronics Applications (MTS-I)
Performed applications support of the AT&T DA204 & DA205, a gigabit/second serializer/ deserializer in Fibre Channel protocol
Performed laboratory testing of devices including: bit-error rate testing with photonic attenuation and electrical testing, PLL lock and latch testing as a function of supply, temperature and data
Assisted Lockheed Martin in thermal/radiation testing for Space Application
Provided applications assistance with customers and provided design feedback
Addressed false transition design issue and PLL lock detect with current controlled (DAC) issue
Supported customers in integrating Fibre Channel SERDES and product
Bell Laboratories Memory Design (TA/STA/MTS-I)
Designed evaluation board for transmitter/receiver Memory Development Laboratory (TA, STA, MTS-I)
Worked in design, electrical failure mode analysis, characterization and layout of High Speed SRAM and DRAM from 64K DRAM to Megabit SRAM densities. Simulation of Cell Stability for DC and AC response of Megabit SRAM
Electrical Design of Memory Circuits including boosted clock row driver and sense amplifier
IBM - High Speed Printer Test and Repair Technician Endicott, NY
Printer Manufacturing 1979 – 1980
Skills:
Java, Microsoft VB6 and Visual Studio 2005 – VB.net, C and C#
User of Spectre, H-spice, Goalie, Celerity, Virtuoso, Caliber, Composer, and other tools
Excellent Unix/Shell (Java, Perl, Awk, R, S, S-plus, C, TCL and shell programming)
Direct interface with End user at customer location
Microsoft 95/98/NT/2000/XP/7/8,10 proficient
TCP/IP 10/100 LAN network design and debug
Oscilloscope, Phase Noise Tester, Rohde & Schwarz CMU, Spectrum Analyzer, Wavecrest Analyzer, Network Analyzer, AWG, Power Supplies, Digitiers, Logic Analyzers, Bit Error Rate Tester and other electrical instruments.
Project Management of Complex Scheduled Problems
Substantial Field/Travel experience/tolerance
Support of represented and non represented employees and contractor
Education:
Muhlenberg Evening College Allentown, PA
Com Science & Physics Major – All 100 & 200 level courses (5) taken with 3.5 average 1980 – 1990
Lincoln Technical Institute Allentown, PA
1977-1979
Interests:
Free Masonry
Volunteer firefighting/rescue
Languages:
English
German
References:
Available on request
Contact this candidate