Materials Science & Engineering Research Leader
Resume:
YAMINI BHALLA
Atlanta, GA Ph.: +1-703-***-**** ********@******.*** LinkedIn
EDUCATION
Georgia Institute of Technology (GT)Atlanta, GA
Master’s in Materials Science and Engineering (GPA: 4.00/4.00)Aug 2025-Present Delhi Technological University (Formerly DCE)Delhi, India Bachelor of Technology in Polymer Science and Chemical Technology Aug 2018- July 2022 CGPA: 9.43/10 (3.97/4.00) Department Rank 1, Received Vice Chancellor’s Gold Medal (Highest Academic Honor). TECHNICAL SKILLS
Material Characterization and Troubleshooting: Impact Testing, FTIR, TGA, DSC, Melt Flow Index, Thermal Analysis Testing, Accelerated Aging Tests, Comparative Tracking Index (CTI), Optical Microscope, SEM, XRD. Nanofabrication & Cleanroom operations: Lithiography, ALD, Denton E Beam Evaporator, RTP, Fumehood, Reactive Ion Etching, SSI RTP, PVD, Sputter Coating, Hall effect, Semiconductor Packaging Design & Simulation Tools: ANSYS (HFSS), COMSOL, Cadence, AUTOCAD Software Proficiency: Microsoft Suite, Life Cycle Assessment, Python, Tableau Quality and Process Improvement: Six Sigma, Design of Experiment (DOE), Statistical Process Control (SPC), Reverse Engineering, Root Cause Analysis (RCA).
WORK EXPERIENCE
Research Assistant, Georgia Institute of Technology, Atlanta, Georgia Aug 2025 – Present
● Working under Prof. Eric M. Vogel on MOS capacitor fabrication in a cleanroom using photolithography, ALD, thermal oxidation, e-beam evaporation, RIE, and CMOS cleaning; verified thin-film and oxide thickness via ellipsometry and optical microscopy.
● Conducted device characterization using probe stations to obtain and analyze current–voltage (I–V) and capacitance–voltage (C–V) characteristics.
● Extracted key device parameters through electrical performance analysis, identifying fabrication-induced variations and opportunities for device performance improvement. Materials Engineer II, R&D, HAVELLS India Ltd, Delhi-NCR, India July 2022- July 2025
● Led process and material optimization for VAVE Jar Collar project using DOE, SPC, and Six Sigma, achieving 20–30% cost reduction. Improved process capability by over 15% with no impact on yield or reliability.
● Developed and qualified eco-friendly, recycled, and sustainable materials, achieving ~30% chemical cost reduction and 30–40% CO footprint reduction, meeting electrical, thermal, and mechanical reliability standards.
● Performed advanced material characterization (SEM, XRD, TGA, DSC, FTIR) across thin films, polymers, ceramics, and metals to support supplier qualification, benchmarking, and COPQ reduction (~20%).
● Conducted Life Cycle Assessment (LCA), carbon-footprint mapping, RCA, and cross-functional sustainability initiatives across 10+ product lines, reducing repeat failures by ~25% and supporting ESG reporting and compliance. ACADEMIC PROJECTS
● Development of Advanced package design, Georgia Institute of Technology Oct 2025 - Dec 2025
• Studied the impact of material selection and design on performance in advanced semiconductor packaging.
• Designed and optimized vias in Ansys HFSS, ensuring ~15–20% reduction in insertion loss through simulation-based optimization. Coursework: Microelectronics system packaging, Electronic Packaging Assembly and Glass Core Packaging.
● Graphene Silicon Schottky Diodes Development, Georgia Institute of Technology Sep 2025 – Nov 2025
• Performed wafer-to-chiplet preparation and PVD thin-film deposition for graphene–silicon Schottky diode fabrication.
• Conducted post-process thin-film characterization using microscopy to evaluate film quality and device structure.
● Silicon Air Battery (Final year project), Delhi Technological University June 2021 - July 2022
• Presented project findings at ICAPIE 2022, the 7th International Conference on Advanced Production and Industrial Engineering.
AWARDS & ACHIEVEMENTS
● Certificate of Appreciation for working on Life Cycle Assessment (LCA) and Carbon footprint mapping, driving sustainability Initiatives HAVELLS India Ltd., India, 2023–2024
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