RFIC/Analog Layout Designer - Senior Level Experience
Resume:
Kevin Molin **** Wildwest Circle, Moorpark, CA ***21 Cell Phone: 760-***-**** ***********@*****.***
Goal: Senior Layout Designer with 12+ years of experience delivering high-performance analog, mixed-signal, RF, and power semiconductor layouts from concept through tape-out. Proven contributor in fast-paced startup and advanced R&D environments, with deep expertise in Cadence Virtuoso, verification, parasitic extraction, and productivity optimization.
Work History
HRL Laboratories August 2025 - Present
Layout Designer Malibu, CA
NDA (Engineering project).
Training in Innovus Implementation System.
Training in FinFET.
Silanna Semiconductor August 2015 – July 2025
Layout Designer San Diego, CA/Raleigh, NC
Worked in a fast-paced startup environment.
Layout of Analog Mixed Signal and digital cells required for high performance DC/DC power converter products.
Worked with TSMC Gen3 0.18u BCD technology.
Worked with custom in house developed 0.18u SOI based power technology.
Tasked with cooperative creation and maintenance of 0.18u CMOS standard cell library.
Produced quality layout for a broad range of designs including high speed digital isolators, Bandgap, ESD, Oscillator, Driver, Controller, Comparator, Fuse, Op Amp and various analog/mixed signal layout designs.
Responsible for coordinating with lead design engineer for routing and verifying top level/macro layout.
Tasked with implementing newly introduced simulation tool Magwel (running High-Side/Low-Side RDSON/Gate-delay simulations on power blocks used in DC/DC converter power products).
In charge of generating and evaluating Silicon Frontline extraction tool RMAP and collaborated with design team to implement strategies for improved layout designs.
Increased personal productivity by over 30% in less than one year.
Responsible for streamlining tape-out procedure and putting together an accommodating layout checklist.
Created and maintained layout team website, document control, project updates and team management.
IO Semiconductor (Sold to Silanna Semiconductor) September 2012 - August 2015
Layout Designer San Diego, CA
Assisted with the layout of high performance, multi-band, multi-mode cellular frontend semiconductor chips by utilizing an-in house developed custom SOI based RF CMOS Technology.
Collaborated on numerous block-level designs such as ESD, Op Amp, Clock, Memory, Controller, Bandgap, Metal and VIA programmability for specific designs.
Tasked with finalizing metal-changes and tape-out of multiple designs in an efficient manner.
Managed directories within Linix/Unix software systems.
Created various designs for testing of products such as CAL structures and Daisy Chains.
Technical Skills:
Fluency in Cadence (Virtuoso, VirtuosoXL, GXL, etc.) and some experience with VCAR.
Knowledge in Unix/Linix and some experience with C++/SKILL.
Fluent in chip verification programs such as Mentor Calibre and Assura.
Experience and knowledge running Silicon Frontline RMAP and Point-to-Point tools.
Experience with Analog layout, and device matching techniques.
Training and experience with Magwel parasitic extraction software.
Experience and knowledge of generating and evaluating Silicon Frontline RMAP.
Training in EDA DxDesigner Pads Flow tool.
Microsoft Programs such as Word, PowerPoint, Access, and developed statistical analysis using Excel. Also experience with AutoCad and Rhino design programs.
Taken number of online Cadence/CAD courses.
Education
San Diego State University August 2005 - May 2009
BA in Economics
Specialty: Economic research and statistical analysis using simple and multiple linear regression.
Woodbury University May 2010 - August 2011
1.5 years in graduate program
Specialty: Architecture research and design for potential sprawl cities. Involved in a creative design project which was inserted into the WuHo building. (building on Hollywood blvd).
Silicon Drafting Institute October 2011 - September 2012
Specialty: Engineering. Integrated Circuit Design and Layout.
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