Design Engineer Electrical Engineering

RAVI TEJA BOKKE

Richardson, TX ***** +1-945-***-**** *********.****@********.*** LinkedIn - Ravi Teja Bokke EDUCATION

The University of Texas at Dallas May 2026

Master of Science, Electrical Engineering GPA 3.7

Relevant Coursework: RF & Microwave Circuits, Analog Integrated Circuit Design, RF & Microwave Systems, RF Amplifier design, PA, Fiber optics and VLSI. Reva University, Bangalore July 2020

Bachelor of Engineering, Electronics & Communication Engineering GPA 3.4 TECHNICAL SKILLS:

Tools: LTspice, Hyper lynx, ADS, HFSS, AWR, Synopsys, APD, Cadence CIS, Cadence Virtuoso, and Microsoft Office (Excel, PPT, Word). Measuring Equipment: DMM, Oscilloscope, Signal generator, Vector Network Analyzer, Spectrum analyzer, Function Generator, Noise Source. Programming Languages: Verilog, C, and Python.

WORK EXPERIENCE

Skyworks Solutions Inc, Cedar Rapids, IA. June 2025 – Present RF Design Engineer Co-op

• Design and development TXDSM MCMs for mid-high band 5G/LTE applications, focusing on RF performance, and layout-driven debugging.

• Performed cascaded EM simulations of MCM and EVM PCB layouts using HFSS, Optimized PA impedance matching in ADS by sweeping ET delay and tuning passive components to improve ACLR and Current efficiency.

• Designed and developed a complete mm Wave Evaluation Board for project, Notch filters and tuned bypass capacitors for up to 6th order Harmonic suppression and Improved TX path Stability at over-temperature via capacitor detuning in feedback path to reduce oscillations.

• Analyzed Pout, Max Iso Power, ACLR, Current, Gain, Noise figure, Tx leakage, and isolation across Rx paths; correlated ATE data with lab measurements. Mistral Solutions Pvt Ltd, Bangalore. January 2021 – July 2024 Senior Analog/RF Design Engineer

• Designed and developed RF components and cascaded circuits including Synthesizers, Exciters, Receivers, Antennas, TRMMs, RF-FE modules with LNAs, PAs, Mixers, DGAs, Phase Shifters, Filters, Diplexers, RF Switches, DACs, ADCs and RF SoCs for radar sub-units in Indian Defense and French airborne systems, performed signal, power, and S-parameter analysis, along with PCB layout and schematic co-simulations using Cadence CIS, APD, Hyper Lynx, ADS, and HFSS, and supported RF-FE tuning and impedance matching for Samsung and TI EVM projects.

• Enhanced RF performance and ensured compliance with EMI/EMC, DO-254 and MIL-STD-461F/G standards for Aerospace and Defense systems.

• Integrated RF-SoCs in digital systems with UART, I2C, SPI, RS422, DDR4, JTAG, and Ethernet PHYs on Intel SoCs, FPGAs, and Microprocessors. Wiwo -Tech Systems Pvt Ltd, Bangalore. August 2020 – January 2021 Hardware Trainee Engineer

• Worked on OrCAD CIS Schematic and Allegro PCB Editor for RF/high-speed layouts across various RF bands and designed custom SAW based Low, High and Bandpass filters for L band using ADS and tested the components physically using RF lab instruments.

• Collaborated with firmware/software teams to develop automated hardware test scripts, improved software quality by reducing manual testing efforts, managed RF budget analysis, Proposal documentation, and finalized project BOM lock. Bharat Electronics Limited, Bangalore June 2018 – July 2018 Trainee Intern

• Designed a Butterworth low-pass filter with 3 dB insertion and 15 dB return loss, ensuring high linearity and RF performance. And analyzed S- Band Phase Shifter & Digital Gain Attenuator using Xilinx Artix-7T EVM and measured S-parameters, Phase, and Amplitude with a VNA. ACADEMIC PROJECTS

Designed 1 Watt Power Amplifier Cadence AWR Microwave Office January 2025 – May 2025

• Designed a Hybrid multi-stage RF Power Amplifier using EEHEMT GaAs transistors with a Class A driver and quadrature-combined Class AB stages, delivering 1 W (30.04 dBm) output at 7 GHz with 21.73 dB Gain. Achieved 30% PAE, 54% Fractional Bandwidth, –12.29 dB input and

–18.5 dB output return losses, with optimized biasing and 320 mA supply current, using a Lange coupler for efficient power. Designed Wilkinson Power Divider Cadence AWR Microwave Office August 2024 – December 2024

• Designed a 3-dB Wilkinson Power Divider using AWR software, achieving accurate impedance matching with optimal performance. Conducted S-parameter analysis, with low insertion loss (-3.1dB), high isolation (45dB) and good return loss (>27 dB) at a 2 GHz center frequency. Designed Wilkinson Power Divider Cadence AWR Microwave Office August 2024 – December 2024

• Designed a 3-dB Wilkinson Power Divider using AWR software, achieving accurate impedance matching with optimal performance. Conducted S-parameter analysis, with low insertion loss (-3.1dB), high isolation (45dB) and good return loss (>27 dB) at a 2 GHz center frequency. Designed Two Stage Amplifier Cadence Virtuoso (130nm IBM Technology) August 2024 – December 2024

• Designed and implemented the schematic, performed hand calculations for transistor sizing, and conducted AC/DC analyses a two-stage amplifier achieving 63.65 dB gain, 72.08 phase margin, 59.55 MHz unity gain, with optimized slew rate, ICMR, CMRR, and low power dissipation. Designed 8-Bit SPI Cadence Virtuoso (62nm Technology) August 2024 – December 2024

• Designed an 8-bit SPI in Verilog, synthesized using a custom 13-cell library in Cadence, and optimized timing with a 45% delay reduction via PrimeTime. Gained full VLSI flow experience through DRC/LVS checks, cell characterization, HSpice validation, and APR using Innovus and verified AWARDS & HONORS

I received four professional awards for Best Performance, Best Paper award at ICRTECE-2020, and Best Team Player at the University level. ACADEMIC PUBLICATIONS

Published a paper on “Designed and Development of IOT Infrastructure for Digital Health Care Solution” ICRTECE-2020.

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