Design Engineer Asic

Stan Bush

PROFESSIONAL EXPERIENCE

ASIC North ***8-Present

Advisory ASIC Design Engineer

Enhanced a Cadence Genus/Innovus flow for designer’s productivity with Make file and consolidated tcl procedures.

o Consolidated multiple vendor PDK choices and implemented multi- voltage/process/temperature compiling with common MMMC file. o Scan Insertion with design rule fixing in Genus. o Spare-Gate implementation in Innovus.

o IO buffer insertion and “fixing placement” with Innovus.

Designed SAR with read/write byte and burst options in asynchronous environment.

Designed DSP function in a multi-task process that re-used hardware and saved 20X area.

Designed SAR controller that operated at 200 MHz. Implemented controls in mixed mode (analog/digital) design.

Timing closure using Cadence Tempus timing tool.

Function verified operational at speed when customer implement hardware.

Designed SAR ADC controller containing DSP algorithm to self-calibrate major carry error.

Design lead for multiple test chips for standard cell, memory, fuse, and IO cells.

Design verified functionality, timing manufacture process and tool compatibility. Generated test vectors for lab testing. Latest version, reduced test interface from 58 pins to 5 by incorporating JTAG Tap serial interface in place of parallel interface.

Designed and implemented a SPI serial interface and controller for stand-alone chip that contained custom analog blocks.

Reverse engineered an end of life product. Developed digital model of 2 custom 2.4 GHz analog blocks. Modeled in Verilog the whole chip and generated testing vectors for production testing.

Timing closure for all designs using Synopsys Prime Time / Cadence Tempus to tape-out approximately 20 chips.

o Read SPEF files generated by layout.

o Used On Chip Variation (OCV) analysis.

o Used Signal Integrity (SI) analysis.

o Analyzed routed gate solution for power. Leakage and Dynamic. o Timed sub-blocks, exported liberty for higher level integration. Take final top level with sub-blocks and exported flat gate level SDF for simulation timing. o Analyze timing reports to identify layout issues such as:

Over and under loaded cells.

Setup and Hold timing violations.

Special timing arcs for min/max delay.

Area and routing density.

Cross-talk

Spare-Gate insertion and locations.

o Used manual and scripted ECO process to correct report violations by resize cell drive strength, inserting/deleting buffers, re-balance load trees, logic cell implementation, manual clock tree skewing. ECO altered net list is given back to the PD to ECO route the adjustments then return new reports to repeat until timing is clean.

o Unsolvable timing violations may need a data path pipeline design change that requires the source RTL modification and re-synthesis. This modification to the source code must be reviewed by the designer/system manager and verified by simulation to insure function remains is in spec.

Technologies include 350, 180, 90, 60, 45, and 14 nm.

Multiple generated and asynchronous clock domain and mixed mode strategies.

Generated Liberty files for customer standard cell product line. Andigilog 2005-2008

Lead Digital System Architect

As Principal Architect of thermal sensor and fan control ASIC product family, produced modular design specifications for off-site design team and coordinated Verilog RTL development. Led verification and layout teams to insure the behavioral Verilog functioned as specified and remained unaltered after post-routed gates were readied for tape out.

Improved acquisition and control hardware design process by creating algorithm which canceled diode resistance during temperature measurement.

Enhanced report quality and permitted post-silicon timing adjustments by designing programmable signaling controls for analog Delta-Sigma interface and post process acquisition data with Second Order Sinc Filter.

Corrected anomalies in device temperature due to band gap temperature drift by developing curve fit hardware processor that self-corrected data with a piece-wise linear lookup table, which was later adapted to compensate for on-chip oscillator error to improve accuracy of TACH report generation.

Eliminated device pin for bypass capacitor with Digital fan lock algorithm, and TACH speed report.

Performed ultra-low power design with clock-gating and reset management between analog and digital system for power cycle and operational sleep states.

Expanded the testability and product personalization with option to perform full memory upload or dump by Master and slave SMBus module design. The upload option allowed for an external ROM to customize device profile.

Conserved size and power with single chip oscillator by designing programmable 256 level PWM fan drive for 8 low frequency and 8 high frequency, improving original concept requiring 3 additional oscillators for the same function.

Facilitated testing and paved the way for product portfolio expansion to 8 ASICs in 2 years by partitioning design into isolated functional IP modules connected by a common internal communication bus.

Minimized silicon cost and reduced digital footprint with RAM-based register mapping and ALU state machine sequence processing.

Reduced production testing times and strengthened system toggle coverage by designing test features including a BIST generator replacing analog data with programmable waveform producing repeatable patterns.

Achieved quick turn product development by incorporating Intel 8051 8 bit microprocessor into design for future products; allowed for functional ROM changes to evolve product avoiding need for new chip design.

Characterized and debugged first silicon with Lab View-based special test environment.

Tape-out 10 chips.

Motorola / Freescale Semiconductor 2000-2005

Principal Integration Engineer / Member of Technical Staff Served as architect of 2 port RAM interface control on 56000 Hawk V2 DSP Core (16/24 bit microprocessor). Consulted with cross-functional teams including DFT, verification, production, systems, analog, and back-end layout to produce high quality and reliable products. Developed system gated clock control and clock network distribution integrating PLL, Scan, Memory BIST, and Logic BIST.

Decreased integration cycle time from 8 weeks to 2 weeks by developing multimode constraints to physically synthesize and verify timing closure using Synopsys Physical Compiler, Prime Time, and Formality 0.25 and 0.18 micron.

Trained junior designers on asynchronous clock domain design practices and system integration with timing closure.

Tape-out 7 chips.

Motorola SSTG 1982-2000

Principal Integration Engineer / Member of Technical Staff Directed 8-member design team and oversaw design of 4 ASICs. Participated in manufacturing and testing of Hi-Reliable Digital systems. Directed new multi-channel receiver circuit board design efforts.

Enabled tracking of 12 independent GPS satellite signals using SPW by designing ASIC that multi-tasked multiple custom DSP algorithms.

Reduced power consumption by a factor as much as 12 in design of clock gate circuit.

Served as lead designer of fault-tolerant aerospace subsystem used to direct data traffic between redundant controller systems. Overcame challenges of digital logic signaling over 15 feet and supply redundancies.

Tape-out 8 chips.

EDUCATION

Bachelor of Science (BS) in Electrical Engineering New Mexico State University, Las Cruces, NM

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