Mixed Signal IC Layout Designer with 3+ Years
Resume:
MICHAEL DUC HO
**** ***** **** **., *****, TX *5013
*************@*****.***
Analytical, detailed-oriented professional with many years of experience in semiconductor industry along with excellent interpersonal, communication and relationship-building skills. Technically skilled – highly proficient in processes and design rules, verification tools, methodology knowledge in Digital, Analog, Mixed Signal, Diff/Pairs, and most layout designs.
EXPERIENCE
4/2024 – 8/2025 MIXED SIGNAL IC LAYOUT DESIGNER, CIRRUS LOGIC
• Work with Global Foundries and TSMC 55nm, 22nm technologies
• Experience with analog layout techniques such as common centroid, matching, isolation, shielding, and the use of dummy devices ( bandgap, ADC/DAC, pad cells, IO cells)
• Work closely with engineers on ESD protection, EMI, latch up prevention, antenna effects for floor planning and post layout extraction simulations.
• Ability to solve design problems while using a combination of technical skills, intuition, and creativity
• Proficiency in floor planning activities with block assembly, and block level routing
• Work on DRC, ERC, LVS trouble shootings and debugging skills from sub-block up to top-level
• Communicate and work well with others in a fast-paced team-oriented environment
2/2021 – 2/2024 IC LAYOUT DESIGNER, IC ENABLE
• Contracted to Micron Technology to layout fast and accurate digital and analog circuits using double patterning proces (SERDES, PLL, Differential Amp, comparator, current mirror, bias circuit). After that continued with series of test chips for Texas Instruments.
• Experience in layout and verification tools Cadence and methodologies for RF/Analog/Mixed Signal ICs.
• Comprehensive understanding of the target process to balance layout and design needs, e.g. crosstalk, RC delay, electro-migration, IR drop, self-heating, shielding, matching, ESD, guard rings and latch up
• Identify quality and reliability improvements in IC circuit and layout design for area, performance, and power specifications.
• Perform design verification (DRC, LVS) flows from sub-block up through top-level
2019- 2021 ELECTRICAL ENGINEER, TALENT 101. Worked as contractor for Texas Instruments on the design of the thermostat using I2C protocol and SPI protocol. Designed RTL and System Verilog for the interface of digital and analog blocks including the output logic and the test modes based on the specs that combine both I2C and SPI protocols together.. Worked on the flow of system verification by building the test vectors, debugging the flow and improving the logic.
1999– 2019 DESIGN ENGINEER, MICRON TECHNOLOGY• Worked with and provided guidance to physical layout designers and monitored the progress of IC layout including floor-planning, placement, and routing. Understood the layout tools: Synthesis, Place and Route, Post-Timing Analysis etc. Worked to improve layout for Electro-Static Discharge ESD, Electro-migration (static and dynamic EM), IR drop analysis, Power Network Analysis, IO pin cap optimization for high speed. Familiar with EMIR tools like Totem, Signal EM, DC EM.
• Designed for size reductions and low power consumptions, high speed data path, IO interface
• Participated in critical design reviews, Failure Mode and Effects Analysis (FMEA), reliability reviews and created the necessary design and product documentations
1990– 1998 ELECTRICAL ENGINEER, TEXAS INSTRUMENTS
• Worked on designing 1M/4M/16M SDR and DDR Read/Write control circuits, output path and data path. Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions. Focused on lower power consumptions, electro-migrations, signal integrity and reliability.
• Worked on Design-For-Testability (DFT), Design-For-Manufacturing (DFM) to increase testing capabilities at frontend, backend and manufacturing sites. Provided design trainings, supports and debugs to Product Engineers and Test engineers at TI global manufacturing sites.
EDUCATION
BACHELOR DEGREE IN ELECTRICAL ENGINEERING, UNIVERSITY OF HOUSTON
• Honor engineering student GPA 3.57
• Tau Beta Pi Membership
• Eta Kappa Nu—electrical engineering honor society
SKILLS
• Strong verbal and written communication skills with the ability to convey complex technical concepts to other design peers in verbal and written form. • Good skills with Words, Excel, Power Point.
• Ability to work in teams and collaborate effectively with people in different functions
• Strong time management skills that enable on-time project deadlines and delivery
• Ability to take the initiative and drive for results with innovations and collaborations.
PROFESSIONAL REFERENCES
Richard Banh
Senior Mixed Signal IC Layout Designer, Cirrus Logic
Cell: 512-***-****
Email: ********@*****.***
Mimi Nguyen
Senior Layout Design Engineer, Intel
Cell: 480-***-****
Email: ****.********@*****.***
Robert Pinkney
Senior Layout Design Engineer, IC-Enable
Cell: 940-***-****
Email: *******@******.***
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