Test Engineer (ATE)

Changiz PIshdad

San Jose, CA ***** 408-***-**** ********@*****.***

Career Summary

Principal Test Engineer with extensive experience in semiconductor product development, ATE (V93000) test solutions, and high-volume manufacturing. Expertise in load board design, DFT/DFM, and yield optimization for FPGA, SoC, and mixed-signal devices. Proven record of cost reduction, accelerated NPI cycles, and successful global test program releases. Strong technical leadership with cross-functional collaboration across design, product, and manufacturing teams.

Professional Experience

Achronix — Senior Test Engineer

2023 – March 2025

Developed and released V93000 test programs for high-power FPGA chips, ensuring full production readiness.

Designed load boards and sockets for high-pin-count devices, including ultra-high-current supply calculations.

Created custom C++ test methods for memory repair and EFuse programming.

Applied DFT principles, improving test coverage and manufacturability.

Negotiated with vendors, purchased ATE hardware, and optimized HTOL chamber conditions for reliability testing.

Supported flip-chip substrate design with IBIS simulation, RLC, IR drop, and thermal modeling.

Marvell Semiconductor (via Aquantia merger)— Principal Test Engineer

2013 – 2022

Delivered full ATE test flow for high-speed chips on V93000, including scan and functional pattern debug.

Directed offshore product transfers and program verification, reducing bring-up time.

Designed and procured load boards and sockets for complex devices.

Negotiated with vendors to achieve cost savings and ensure high-quality hardware.

Evaluated and introduced yield-enhancement tools, improving test efficiency.

Zenverge — Senior Test Engineer

2009 – 2013

Managed NPI test development for mixed-signal and digital devices, from wafer sort to final system test.

Improved yield and quality at wafer, package, and assembly levels.

Designed qualification boards for HTOL stress testing, calculating chamber conditions for target lifetimes.

Led cross-site collaborations with fabs and assembly houses in Taiwan and Korea.

Authored and enforced DFT documentation, improving standardization across teams.

Earlier Experience

Held engineering and leadership roles at Analogix Semiconductor, Genesis Microchip, and Centillium Inc. Responsibilities included ATE program development, test optimization, yield improvement, and team management. Contributions spanned advanced SoC, product lines, with emphasis on reducing test costs, enhancing reliability, and delivering high-volume production solutions.

Education

B.S., Electrical Engineering — University of Science & Technology, Tehran, Iran

Tools & Skills

ATE Platforms & Tools: V93000, Smart Scale, Perl, C, C++

Processes: DFT, DFM, NPI, HTOL, reliability testing, yield enhancement

Other: Vendor negotiations, cross-functional leadership, offshore program transfer, cost reduction strategies

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