Test Engineer (ATE)
Resume:
Changiz Pishdad
San Jose, CA*****
********@*****.***
CAREER SUMMARY
Highly motivated, self-directed Electronics and Semiconductor Technology professional with twenty years of experience managing all aspects of product development & qualification, product testing, yield, quality improvement, and client support
Experience includes leading blended teams, developing and managing budgets, devising timelines, monitoring project standards for all deliverables, creating strategies, overseeing technical design and development, project integration and implementation, documentation, record keeping, training, and maintaining quality assurance throughout the entire project
PROFESSIONAL EXPERIENCE
Jan 2023 – March 2025 Achronix, Santa Clara, CA
Senior Test Engineer
Completed all ATE (V93K) test programs for high-power FPGA chips to ensure quality delivery
Designed all load boards, including calculation of cap values for ultra-high current supplies, and corresponding sockets for high-pin count, high-speed chips
Responsible for sort and packaged test program release locally and offshore
Applied Design-for-Testability (DFT) and Design-for-Manufacturing (DFM) principles to improve test coverage and manufacturability
Developed required custom test methods (C++) for complex blocks, like Bram memory repair, Chip ID burn to EFuse memory
Negotiated with vendors and purchased all ATE required hardware
Optimized HTOL chamber conditions and board configurations to meet target life expectancy benchmarks, ensuring compliance with customer-specific reliability requirements
Oversaw flip chip substrate design, performing critical modelling tasks including IBIS simulations, RLC extraction, IR drop, and thermal analysis to support robust manufacturing outcomes
June 2013 – Jan 2023 Marvell Semiconductor (adquirid Aquantia), Santa Clara, CA
Senior Test Engineer
Developed a program for new high-speed SoC chips
Collaborated with the engineering department on innovative test design and coverage
Responsible for product transfer and test program verification in both local and offshore facilities
Managed and completed an ATE test program for a complex high-power, high-speed chip
Evaluated and purchased cost-effective yield enhancement tools
Designed and ordered all ATE boards and their appropriate sockets
Directed negotiations with all required vendors on price reductions and quality
Achieved on-time completion of full test flow utilizing V93K tester by implementing and debugging scan and various functional patterns to improve yield and release to production ahead of schedule
Dec 2009 – June 2013 Zenverge, Santa Clara, CA
Senior Test Engineer
Managed all customer deliveries from sort, assembly, ATE, and bench, to bake and ship
Improved and resolved yield and quality-related issues at the assembly, wafer, and package level
Completed several NPI processes for mixed-signal and digital products
Managed engineers on Product and Test teams who were working on multiple simultaneous projects
Worked with Taiwan, Korea wafer fabs and assembly houses on up to 55nm technology on high volume wafer and package manufacturing
Involved in, and managed flip chip substrate design, including all required modelling (IBIS, RLC, IR_DROP, and thermal) and manufacturing
Created DFT and DFM documents from scratch and enforced them on a daily basis
Managed and designed all qualification boards based on HTOL machine’s spec, calculating the chamber stress condition settings for specific life expectancies
Managed and completed ATE test program for a complex high-power high-speed chip
Evaluated and purchased cost-effective yield enhancement tools
Designed and ordered all ATE load boards and their appropriate sockets
Directed negotiation with all required vendors on price reductions and quality
Settled long-term relationships with tier 1 vendors to deliver the highest quality products
Nov 2007 – Aug 2009 Analogix Semi, Santa Clara, CA
Statt Test Engineering Department
Managed test/product teams for new and ongoing project developments, enhancing process quality by applying the best available approaches and tools in the market
Worked with design teams from the first steps of new designs to implement more testability features into the chip, like adding internal loop back, which cut the costs by adding better coverage
Managed the subcontractors, leading periodic meetings with them, discussing issues, and scoring them based on their quality of service and price
Monitored production yield and progress using specially implemented software, minimizing response time to any production-related issues
Created reliable and accurate schedules for new projects and their delivery dates to customers based on the input from design, marketing, and other involved teams
Participated in test/product seminars to update the team with the latest tools in the market for better efficiency
March 2002 – Nov 2007 Genesis Microchip, Santa Clara, CA
Manager of Test Engineering Department (Oct 2003 – Nov 2007)
Responsible for reducing ATE test program time by 30-50 percent, cutting testing costs by over half a million dollars per quarter
Developed a special ATE wafer sort program using Synopsys Tetramax tool for overall yield enhancement, finding the root cause of low yield lots, and failure analysis purposes
Designed new test methodologies and transferred them to test engineers for better efficiency
Acquired good knowledge management within the team
Newly achieved knowledge and skills were passed to other members by performing internal classes and presentations
Participated in weekly meetings among U.S, Canada, and India offices so design, marketing, and test/product teams can discuss their project progress details
Created and updated lists of new designs based on the company roadmap, assigning them to team members in advance so they could study and learn about their projects and prepare the necessary hardware before the project start
Worked closely with the team members and checked the progress during the different phases of their projects to make sure the job is delivered on time
Staff Test Engineer(March 2002 – Oct 2003)
Responsible for program development for new SoC chip sets, including ADC, DAC, and high-speed interfaces like LVDS, TMDS, RSDS and DVI for flat panel and HDTV controllers
Worked with the engineering department on new test design and coverage
Responsible for product transfer and test program verification in both local and offshore facilities
Aug 2000 – March 2002 Centillium Inc., Fremont, CA
Staff Test Engineer
Developed and implemented test procedures and test programs for high-end DSL and VOIP chips using embedded firmware commands and C programs
Worked with local test houses and offshore facilities to transfer programs and train engineers on test coverage and specifications
Worked closely with design engineers to optimize test coverage and reduce test times
EDUCATION
BS, Electrical Engineering, University of Science & Technology, Tehran, Iran
Graduated Summa Cum Laude
TOOLS & SKILLS
V93K, Smart Scale, PERL, C++, semiconductor, manufacturing, testing, product engineering, C, IBIS simulations, thermal analysis, NDT, EBEAM, FIB, ADC, DAC, LVDS, TMDS, RSDS, DVI, process improvements, leadership, team leadership, business strategies/operations, written / verbal communication, presentations/ seminars, vendor negotiations, critical problem-solving, client relationships, cost reduction/containment, analytical skills, cross cultural communication
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