Technician Ii Mixed Signal

Matthew Neugyn

*******.******@*****.*** 714-***-**** Santa Ana, CA

WORK EXPERIENCE

ANALOG DEVICES TECHNICIAN II San Jose, CA May 2020 - May 2025

• Designed analog blocks on both P90 and S18 process. Working closely with circuit designers and layout chip leads on multiple and different projects locally and remotely. Projects include mixed signal and custom analog sub blocks, placement and integration of blocks and top level routing. Such blocks included of LDO, BIAS, and more. Performed ECOs for better performance and reliability, such ECO included of widening of power and ground metals, putting guardrings to satisfy latchup, changing devices and better matching for better performance. Debugging and fixing top level layout's LVS, DRC, Latchup, Antenna and density check. All verification were done with Calibre and all projects were done with Cadence 6.1

MOVANDI STAFF LAYOUT DESIGNER Irvine, CA Mar 2018 – Aug 2018

• RFIC 28GHz project for 5G 40nm CMOS TSMC pdk using PVS verification tool for LVS, ERC, and DRC. Specific tasks were Unit cells, Current Mirrors, Logic Cells for bias block. Checking and solving all EM, Shielding, and IR Drop issues for Power, Ground, and all critical signal connection for all sub-cells, sub blocks, and top blocks. WESTERN DIGITAL IC LAYOUT DESIGNER (Kelly Service Contractor) Milpitas, CA Feb 2017 – Mar 2018

• Constructing Global Reference Circuit for 3D 24nm 64 layer NAND Technology. Participated in many structures for ReRAM, BiCS5, and Storage Class Memory. Used Calibre DRC and Hercules LVS to debug and fix layout issues of block and cell level while following schematic.

SPATIAL LINK MASK DESIGNER Irvine, CA Aug 2016 – Feb 2017

• Performed layout analog mixed signal chip using TSMC 65. Implemented layout techniques for device matching such as cross-quad, common centroid and interleave, shielding, and capacitance reduction. Maintained constant dedication to quality and accuracy to ensure jobs were completed correctly with the design engineers to provide initial floorplans. Block includes: ADC and DAC EDUCATION SILICON DRAFTING INSTITUTE ADVANCED BiCMOS MASK LAYOUT DESIGN San Jose, CA Jan 2016 - Aug 2016

IC LAYOUT TOOLS

Cadence Virtuoso Layout Editor, Cadence Virtuoso XL Editor, Cadence Virtuoso Schematic Composer, PCELL utility. Cadence Assura DRC and Soft Check Rule with LVS, Calibre DRC and Hercules LVS.

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