Product Development R D

Manjyot Saini (Manu)

916-***-**** ️ *************@*****.*** linkedin.com/in/msaini916

Semiconductor Engineer with 8+ years of experience in product development, yield improvement, and process optimization across advanced R&D and high-volume manufacturing. Proven track record in dielectric deposition, automated test development, SPC monitoring, and defect debug, with expertise spanning fab operations and silicon productization. Skilled at leading cross-functional teams, driving data-driven solutions, and delivering measurable improvements in time-to-yield, fab productivity, and system reliability. PROFESSIONAL EXPERIENCE

Intel, Folsom, CA — Lead Product Development Test Engineer August 2021 – PRESENT

● Developed and deployed automated test programs from TPTorrent; using python (PyTorch/TPIE) on Linux platforms for HDMx.

● Analyzed test data/bins using SQL and PowerBI, enabling root-cause diagnosis of silicon defects within Trace and contributing to a 22% reduction in time-to-yield.

● Collaborated cross-functionally with validation, DFT and design teams to accelerate debug closure leveraging beyond compare, achieving a 30% improvement in issue resolution time.

● Led lab operations for power-on, increasing coverage and first-pass success rate for multiple new product lines.

● Enhances documentation and process standardization for test flows, decreasing onboarding time for new engineers/hardware technicians by 40%.

Intel, Hillsboro, OR — Lead Process Engineer

December 2019 – August 2021

● Led metrology qualification and debug for new tool installations and R&D line expansion, accelerating ramp-up by 35%.

● Conducted experiments on dielectric deposition and wet etch processes (CVD, VPE, PCD and ALD, MOCVD), validating tool readiness and contributing to 18% faster process changeover.

● Created automated data analysis scripts and used SQL to monitor SPC violations, improving issues detection by 28% across critical layers.

● Partnered with field service engineers to develop fault isolation strategies, reducing equipment related yield loss by 65%.

● Authored process documentation and created tool specific recovery procedures, improving overall fab stability and technician response efficiency.

Intel, Hillsboro, OR — Lead Process Engineer

December 2017 – December 2019

● Acted as the primary process owner for statistical out of control events, reducing rework by 75% through targeted recovery plans.

● Supported agile development cycles by integrating inline test data for preventive maintenance metrics, reduced tool downtime by 30%.

● Led cross-site technical reviews and vendor engagement for equipment benchmarking and best practice sharing, contributing to 15% higher fab productivity.

● Managed job assignments between engineers, technicians and vendors during critical high-volume ramp-ups. TECHNICAL SKILLS

Data & Automation: Python (PyTorch, TPIE), SQL, Power BI, SPC, Virtualization (OpenShift) Test & Debug: PyTorch/TPIE, Beyond Compare, TRACE, TPTorrent, ULTRA, Power BI, OpenShift Virtualization, MS SQL Process & Equipment: Dielectric Deposition (CVD, MOCVD, PECVD, LPCVD, ALD, VPE, PVD), Wet Metrology/Etching, Vector/Sabre, AHM HXi, Nexus, 2300

Core Competencies: R&D HVM Process Optimization, Testing /Debugging, Data Analysis, Fab Productivity, Cross-functional Leadership

EDUCATION

University of San Francisco, San Francisco, CA Master of Science in Computer Science Arizona State University, Tempe, AZ Bachelor of Science in Biological Sciences

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