Design Engineer Hardware

Kevin M. Rishavy

**** ********* ****** *****, ******** Springs, CO 80906

Home: 719-***-**** Cell: 719-***-****

LinkedIn: Kevin_Rishavy Email: ********@*******.*** Summary

Design engineer with extensive experience in PCB’s, FPGA’s, and analog/digital system design. Skilled in creating high-speed networking and storage solutions, power control, and embedded CPU subsystems. Hands-on in lab debug, compliance testing, and product support. Passionate about developing reliable hardware systems and able to collaborate with cross- functional teams to bring products from concept to production. KEYSKILLS

PCB Design & Layout Oversight: Cadence Allegro, Orcad, Mentor Pads

FPGA/ASIC: VHDL, Verilog, SystemVerilog; Xilinx, Intel/Altera, Lattice

High-Speed Interfaces: PCIe, Ethernet, USB, SAS/SATA, DDR2/3/4, I C, SPI

Analog & Power: Power modeling/DFP, DACs/ADCs, regulators

Debug & Test: Oscilloscopes, logic analyzers, protocol analyzers

Collaboration: Hardware/software bring-up, manufacturing/test RELEVANT EXPERIENCE

Microchip Technology — Senior Technical Staff Engineer Colorado Springs, CO 2022–2025

Lead design/debug for high-reliability SAS/SATA controllers.

FPGA/RTL development, firmware integration, and processor debug.

Oversight of cross-site teams (San Jose, Burnaby, Bangalore).

Hands-on with lab debug using oscilloscopes, analyzers, and compliance tools. SEAKR Engineering — Senior Electrical Engineer

Centennial, CO 2020–2022

Designed JESD204B/C high-speed serial interfaces for satellite comms.

Implemented 10G Ethernet FPGA designs (Xilinx Versal, UltraScale).

Led build-to-print test and debug of satellite telemetry processors. Viking Enterprise Solutions (Sanmina) — Senior Systems Engineer Colorado Springs, CO 2015–2019

Developed high-capacity storage systems: PCB design, FPGA selection, RTL coding, and system bring-up.

Directed PCB layout, verified designs in lab, and supported manufacturing. Avago/LSI Technologies — Principal Design Engineer Colorado Springs, CO 2012–2015

FPGA emulation of next-gen RAID controllers using Altera platforms.

High-speed interface design and power optimization for storage controllers.

Extensive debug with logic analyzers, scopes, and protocol analyzers. ON Semiconductor — Staff Design Engineer

Colorado Springs, CO 2007–2010

Developed SoC with ARM Cortex-M3, flash, and analog front-end.

FPGA emulation and power management design.

Earlier Experiences

Design engineer roles at Hittite Microwave, Marvell/Intel, Symbios Logic, Philips, and Honeywell covering analog IC design, FPGA/ASIC, DSP, and PCB hardware development. EDUCATION & TRAINING

MSEE, University of Colorado Thesis: Data Conversion ASIC for CD-ROM

BSEE, University of Colorado

Post-Grad: Analog/Mixed-Signal IC Design, PCIe/SAS/SATA protocols (MindShare)

Hobbies: Amateur Radio (N0NKF)

PATENTS (Selected)

CMOS Driver for Fast Single Ended Bus (U.S. Patent 5,576,640)

Pipelined Combination and Vector Signal Processor (U.S. Patent 5,303,172) Awards (Selected)

System-level troubleshooting and quality system solutions: Intel - Divisional Recognition Award

“Providing Maxon with a Platform Solution to the Manitoba 32KHz Oscillator Issue” Intel - Spontaneous Recognition Award

“In recognition of contributions to bringing up ChipWatcher capability in Manitoba” Intel - Divisional Recognition Award

“Eastward Gasket Architecture, achieving better than expected performance in Manitoba”

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