Process Engineer Data Entry

PONY TSAI

********@*****.*** https://www.linkedin.com/in/pony-tsai-600a09139/ +1-623-***-**** Rome, NY ABOUT ME

Semiconductor Process Engineer — Results-driven senior lithography and mask process engineer with 8+ years of experience at TSMC, leading advanced node technology ramp-up in high-volume manufacturing. Proven track record in the successful startup of two state-of-the-art fabs (Fab 18 in Taiwan and Fab 21 in the U.S.), with expertise in mask inspection, process optimization, and cross-functional team training. Strong background in tool qualification, false defect reduction, and standard operating procedure design for global teams. PROFESSIONAL EXPERIENCE

TSMC F21 - Senior Process Engineer; Phoenix, AZ May 2021 – Present

● Designed and implemented an overseas EUV mask transportation flow, reducing lead time from 7 days to 3 and cutting logistics costs by 80%.

● Achieved 85% tool throughput and 100% compliance by leading EUV mask inspection tool qualification.

● Supported Fab 21 start-up in Arizona through training programs for new hires and hands-on qualification of technicians and engineers in advanced lithography processes.

● Translated and optimized SOPs for the mask team, significantly improving operational efficiency and reducing onboarding time.

TSMC F18A - Senior Process Engineer; Tainan, Taiwan Jan 2019 – May 2021

● Partnered with IT to develop an auto recipe creation system, saving 1.5 hours per tool per day in technician time.

● Collaborated with equipment vendors to implement process improvements (CIPs), increasing tool availability by 7%.

● Boosted mask writer capacity by 4 pieces/day by analyzing and matching capacity and quality between secondary writers.

● Led start-up of mask team tooling for TSMC’s third advanced Mega Fab in Taiwan, including first reticle inspection tools from KLA (KT670) and Lasertec (X8U), and supported first-batch training for operators and engineers. TSMC F12B - Process Engineer ; Hsinchu, Taiwan Sep 2017 – Jan 2019

● Transferred N5 technology from R&D to HVM environment.

● Enhanced N12 mask manufacturing by reducing wafer defects and optimizing SPC chart monitoring.

● Maintained chip quality for EUV N7+ production—TSMC’s first technology node introduced EUV technologies.

● Conducted photoresist qualification and cost analysis for new applications, contributing to material cost reduction and process optimization for N7+ node technology.

EDUCATION

National Taiwan University, Chemical Engineering MS Taiwan May 2017 Major: Biodegradable materials, Process Flow Optimization, Protein Coating Biomaterial Analysis GPA: 3.5 / 4.0 Research Topic: A simple aminomalononitrile assisted coating with bioactive molecules for enhancing cell affinity on biomaterials

National Taipei University of Technology, Chemical Engineering and BioTechnology BS Taiwan June 2015 Major: Biodegradable polymers, Process Optimization GPA: 3.8 / 4.0

● Academic Excellence Award, NTUT (2014 & 2015)

● Golden Hand Award, NTUT (2015)

SKILLS & INTERESTS

Interests: Swimming, Biking, Hiking, Traveling, Mandarin and English Teaching, Cooking Languages: Native Mandarin speaker; Fluent in English Technical skills: Semiconductor Manufacturing, Lithography, Process Optimization, Project management, SPC, EUV Reticle Inspection, Defect management, Root Cause analysis

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