C++ Ph D

Ali Poursepanj, Ph.D.

US Ci zen Aus n, TX 787**-***-*** 4253 **********@*****.***

linkedin.com/in/ali-poursepanj

Austin, Texas

PERFORMANCE ARCHITECT

Performance Architect with extensive experience with developing workload characteriza on and workload analysis for be er performance and power. Proven ability to build models of CPUs and SoCs for performance projec on and bo leneck analysis. Known as a skilled problem solver with the a en on to detail, accuracy, communica on, and interpersonal skills to be an effec ve leader. Recognized as a strong individual contributor and as a builder of teams with the ability to collaborate with diverse stakeholders including internal and external customers to drive results. AREAS OF EXPERTISE

Hardware Architecture Microarchitecture Pla orm Architecture System Architecture Computer Architecture SoC Benchmarking Debugging Performance Engineering Performance Modeling

Performance Tes ng Workload Modeling So ware Engineering Design Trade of Analysis

Simula ons

Sta c Timing Analysis Semiconductors Embedded Systems Microprocessors TLM System C C

C++ Unix

PROFESSIONAL EXPERIENCE

Self Employed - Mentor and Consultant November 2023 - Present

- Consul ng in the

area of CPU and SoC model development and analysis. That includes CPU pipeline and SoC

components such as cache, data fabric, memory controller, DDR memory, coherency protocol.

- Workload characteriza on and bo leneck analysis.

- Help ex co-workers, family and friends with career coaching and mentoring ADVANCED MICRO DEVICES, Aus n, TX October 2021 – November 2023 SoC Power and Performance Modeling Lead

Led power and performance analysis and iden fied bo lenecks of CPU and SoC architecture and systems resul ng in an improvement in performance of up to 20%.

● Built analy cal and simula on models for power and performance projec on and analyzed them for be er results.

● Established the correla on between measured silicon numbers against performance model projec ons for various metrics.

● Developed workload characteriza on of AI, ML, DP, and other customer workloads by profiling their traces and iden fying their bo lenecks.

IBM CORPORATION, Aus n, TX June 2019 – October 2021 Chief SoC Performance Architect, System Modeling Team Lead

Led a team of 1-5 performance engineers to develop and validate system performance models, validate project performance, conduct bo leneck analysis, and establish performance Improvements. Examined the best methodologies for current and next genera on CPU and SoC architecture performance modeling and analysis including model development, workload characteriza on, and analysis methods. Developed simula on models and iden fied representa ve workloads to project SoC performance.

● Profiled traces and compared their simula on numbers against measured numbers in silicon which showed a 20% difference in results.

● Created new traces between simula on projec on and measured numbers in silicon resul ng in a reduc on from 20% to 5% numbers.

● Produced trace sampling to find the smaller size trace and be er representa veness of the workload as previously done for my PhD disserta on and published papers on the topic.

● Using both simula on and analy cal models to project performance, compared these two methods for faster performance projec on.

NXP AUTOMOTIVE, Aus n, TX June 2017 – July 2019 Senior Performance Verifica on Lead Developed and analyzed memory controller model bandwidth and created a list of op ons for best performance resul ng in increased memory bandwidth of 50%. Studied micro-architecture documents, developed data flows for different applica ons, defined various data flow parameters, developed micro benchmarks, and ran them on the RTL verifica on test benches and other performance models. ● Developed micro-benchmarks and other performance tests verifying the performance of automobile SoCs.

● Studied the SoC bo lenecks by developing the relevant performance tests and ran them on the SoC simula on models.

● Educated the performance verifica on teams with performance architecture, performance verifica on, and bo leneck analysis.

ENCORE SEMI, Aus n, TX December 2016 – June 2017 Senior Performance Architecture Consultant: Assisted Encore Semi with System Performance Modeling (SPM) services. INTEL CORPORATION/LSI LOGIC, Aus n, TX June 2014 – December 2016 Collaborated with internal and external customers to iden fy bo lenecks and create the best architecture for highest performance and lowest power resul ng in $100M design win. Atom CPU Lead Performance Architect and Manager Spearheaded development of CPU and SoC performance models a er LSI purchase by Intel and delivered them to external customers. Led a team of 10-12 Hardware Engineers. Managed and ac vely par cipated in the CPU model development using C++, architecture explora on, architecture valida on, pre and post silicon power and performance analysis, SoC teams support, workload characteriza on and tracing.

● Helped secure ~$100M design win by working closely with the internal and external customers and vendors to understand technical requirements and communicate them with the team. ● Improved company-wide performance modeling and valida on methodology by ac vely par cipa ng in various work groups and demonstra ng ac ons needed to be completed. LSI CORPORATION, Aus n, TX April 2008 – June 2014 Dis nguished Engineer and Modeling Lead Developed an improved system performance model that corrected bo leneck issues that improved performance by 20-50%.

Individual contributor and team lead in developing system performance models in C/C++, SystemC/TLM 2.0, and Synopsys Pla orm Architect for performance analysis of SoC products. The models included ARM processor cores, ARM coherent interconnects, dedicated hardware engines, I/O devices, buses, caches, and memory controllers.

● Key contributor to design wins by enabling customers to es mate their in house applica on performance. Developed methodology for modeling and analysis of customer applica ons before so ware simulators became available.

● Improved LSI compe ve posi on by analyzing performance of standard benchmarks such as Dhrystone, Lm Bench, EEMBC, and customer specific customized benchmarks.

● Determined and resolved bo leneck of a baseband processor chip by using Synopsys Pla orm Architect.

● Improved memory bandwidth by using carbonized memory controllers in the SoC performance model.

FREESCALE SEMICONDUCTOR, Aus n, TX November 2004 – April 2008 Senior Member Technical Staff Served as an individual contributor and team lead in support of architecture performance analysis of PowerQUICC and P4080 SoC products. Used in-house C++ and SystemC based modeling tools to analyze performance of SoC systems.

● Detected and resolved serious bo lenecks before tape-out by developing transac on level models for architecture and applica on models. The SoC models included processor cores, caches, busses, DDR2 and DDR3 memory subsystems, Ethernet, Quick Engines, PCI, security devices, pa ern matching engines, arbiters, and bridges.

EDUCATION

Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering The University of Texas at Aus n, Aus n, TX

Master of Science (MS), Electrical and Computer Engineering The University of Texas at Aus n, Aus n, TX

Ali Poursepanj **********@*****.*** Page Three

PROFESSIONAL ADDENDUM

Patents

Awarded five patents and numerous inven on disclosures around microprocessor design and high speed traffic management.

● Method and system for selec ve serializa on of instruc on

● Method and system for single cycle dispatch of mul ple

● Method and system for single cycle dispatch of multiple instruction in a superscalar processor system

● Method and apparatus for managing the power consumption of a data processing system

● Frame mapping schedule

● System and method for verifying processor performance Publica ons

● Ali Poursepanj, D. N. Jayasimha, “Mul core SoC Performance Modeling and Analysis”, ARM Technology Conference, October 2013.

● Ali Poursepanj, “Experience from the Field, Building SoC Architecture Performance Models using In-house and 3rd Party IPs, “Design Conference, SystemC User Group, June 2013. ● Ali, Poursepanj, Anthony Fama, “SoC Architecture/Performance Modeling using SystemC/ TLM-2.0, a Case Study using Synopsys Pla orm Architect”, Synopsys User Group (SNUG) Conference, 2012. ● Ali Poursepanj, “ A Common System Memory Model for SoC So ware and Architecture Models using a SystemC/TLM-2.0 interface”, DVCON SystemC User Group, February 2011.

● Ali Poursepanj, “Performance Analysis of Mul -core SoC Systems”, Embedded System Conference, April 2004.

● Ali Poursepanj, “Benchmarks Rates Switch Fabric Performance”, Computer Design, December 2003.

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