Electrical Engineering Hands-On

Chi-Yuan Jan

**** ****** **. *********, ** ***** 206-***-**** ****************@*****.***

www.linkedin.com/in/chi-yuan-jan-12079b269/

Summary

Graduate student in Electronic and Electrical Engineering with a strong foundation in digital IC design and a growing focus on deep learning. Experienced in RTL coding, FPGA implementation, verification

(CDC, SystemVerilog), and physical design flow (APR, full custom design). Recently a computer-vision paper published at ICIP 2025. Passionate about the convergence of AI and hardware acceleration, especially in the context of transformer-based models. Strong problem-solving skills and eager to contribute to challenging hardware design engineering roles. Open to relocation. Education

NATIONAL YANG-MING CHIAO-TUNG UNIVERSITY, HSIN-CHU, TAIWAN

• B.ENG IN ELECTRONIC AND ELECTRICAL ENGINEERING Sep 2019 ~ Jun 2023 o GPA 4.03/4.3

• M.ENG IN ELECTRONIC AND ELECTRICAL ENGINEERING Sep 2023 ~ Jan 2025 o Paper accepted on ICIP 2025

Skills & Abilities

· Languages & Scripting:

C, C++, Python, Matlab, Bash

· HDL & Hardware Design:

Verilog, SystemVerilog, SystemC, RTL Design, CDC,

FSM, Computer Architecture (Pipelineing, Risc-V,

Cache, ISA design)

· Tools:

Vivado, Hspice, LTspice, innovus, Synopsys Design

Compiler, ModelSim

· Machine Learning / AI:

PyTorch, CNNs, RNNs, Transformers, Model

Quantization, Computer Vision

· Others:

FPGA experience

Full custom layout experience

· Language:

Mandarin (Native), English (Professional

Proficiency)

Project

• CNN model Deployment on FPGA board– Quantized a CNN model and implemented it on FPGA for real-time image inference.

• FPGA-Based Game System (Academic Project)– Built a Verilog-based 2-player PvP game with display and input control.

• Custom CPU with AXI4 Bus– Designed a RISC-V-compatible 5-stage pipelined CPU with AXI4 interface for DRAM access; implemented from RTL to layout

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