Design Engineer Digital

Sumukhi Nandam

*********.******@*****.*** 858-***-**** San Diego, CA linkedin.com/in/sumukhi-nandam/ PROFESSIONAL SUMMARY

Results-driven Design Engineer with strong expertise in digital design, RTL development, and timing optimization. Proficient in Verilog, VHDL, and System Verilog, with hands-on experience in ASIC synthesis, static timing analysis (STA), and low-power design. Skilled in using Synopsys and Cadence EDA tools for design, verification, and physical implementation. Adept at developing high-performance circuits, optimizing power, area, and speed, and ensuring functional and timing closure. Passionate about advancing semiconductor technologies through continuous learning and industry engagement. EDUCATION

Master of Science in Electrical and Electronics Engineering Aug 2022 - Dec 2024 San Diego State University, San Diego, CA

Bachelor of Technology in Electronics and Communication Eng Aug 2017- Sep 2021 Jawaharlal Nehru Technological University Kakinada, India SKILLS

ASIC & VLSI Design

• RTL Design, Gate-Level Simulation, Digital Synthesis, Testbench Development

• Static Timing Analysis, Low-Power Design, Circuit Modeling, Low-Power Design Techniques

• Physical Design (Floor planning, Placement & Routing), Clock Tree Synthesis (CTS) EDA/CAD Tools & Simulation

• Synopsys Design Compiler, Cadence Innovus, Synopsys PrimeTime, Mentor Graphics,

• Cadence Virtuoso, HSpice, Xilinx ISE Design Suite, Multisim, Spectre, ModelSim, Xilinx Vivado Hardware Description & Verification Languages

• Verilog, VHDL, System Verilog, UVM

• Functional Verification, Coverage Analysis

Programming & Scripting

• Python, TCL, C, C++, Assembly Language, MATLAB

Communication & Organizational Skills

• Teamwork, Technical Documentation, Report Writing

• Problem Solving, Mentorship, Decision Making

EXPERIENCE

Digital MAC Unit Design & Analysis (Project) Oct 2024 - Dec 2024 SDSU, San Diego, CA

• Designed parametric multipliers and adders using Verilog RTL in Synopsys Design Compiler, improving design efficiency by 30%.

• Designed and implemented effective test benches for functional validation, achieving a 30% reduction in simulation errors.

• Performed timing analysis and optimization using Cadence Innovus, reducing critical path delays by 15%.

• Executed Place and Route (PnR) using Cadence Innovus and iSpatial, optimizing layout for area, power, and performance.

• Conducted floor planning and power optimization, addressing IR drop mitigation to enhance chip-level reliability and efficiency.

• Utilized Cadence Tempus for static timing analysis (STA), ensuring design robustness across multiple process corners. High-Speed FinFET Op-Amp (Project) Jun 2024 - Sep 2024 SDSU, San Diego, CA

Engineered a high-speed operational amplifier utilizing FreePDK15 FinFET technology, achieving a 35% performance improvement in gain, bandwidth, noise, and stability.

• Performed Monte Carlo simulations, resulting in a 20% increase in circuit stability and consistency across process variations.

• Enhanced analog circuit efficiency by optimizing key performance metrics with HSpice, leading to improved functionality and reduced design errors.

Engineering Assistant – Digital Systems Jul 2023 - Dec 2024 SDSU, San Diego, CA

• Supported course instruction in digital system design, assisting with RTL development, simulation, and debugging using VHDL/Verilog, enhancing students' understanding of digital logic concepts.

• Led laboratory sessions with FPGA boards and advanced EDA tools (Synopsys, Xilinx, Cadence), guiding students through hands-on digital design practices.

• Taught basic timing analysis and performance optimization techniques, improving student outcomes in digital systems coursework. CubeSat Design Intern Apr 2020 - Jul 2020

NPHSAT Systems Pvt. Ltd, India

Led the design of a miniaturized CubeSat using MATLAB and HFSS, achieving a 45% reduction in deployment cost by optimizing payload mass.

• Collaborated with multidisciplinary teams to develop critical satellite subsystems, including power, communication, and altitude control systems, achieving a 20% increase in system reliability.

• Applied CAE/CAD tools to optimize system-level design and improve component integration. Smart Agriculture System with VEGA Processor on Artix-7 FPGA, Design Team Lead Aug 2019 - Mar 2020 Swadeshi Microprocessor Challenge, India

• Led a design team to develop a smart agricultural solution leveraging the indigenous VEGA processor.

• Developed key system components for weather forecasting and warehouse maintenance on a Xilinx Artix7-35T FPGA board.

• Achieved recognition as a Quarter Finalist in the challenge organized by the Ministry of Electronics and Information Technology, Government of India.

Signaling and Digital Systems Networking Intern May 2019 - Aug 2019 South Central Railway, India

• Coordinated Centralized Traffic Control and Communication-based Train Control with Multisim and Xilinx Vivado, boosting operational efficiency by 25%.

• Collaborated with engineers to design and deploy PLC-based systems, improving Digital Axle Counter reliability by 69% through Electronic Interlocking in railway signaling and control.

• Participated in on-site training to gain hands-on experience with signaling equipment, enhancing practical skills in circuit modeling and basic static timing analysis.

CERTIFICATION

• Digital Design and Verification – InSkill

• Sensors and Circuit Design - Coursera by UC Boulder

• Artificial Intelligence for Everyone - DeepLearning.ai

• IoT and Embedded Systems - Coursera by UC Irvine LEADERSHIP AND ADDITIONAL EXPERIENCE

Technical Research & Volunteer Work, SDSU

• Currently engaged in research and volunteer work at SDSU focused on the ASU PDK 7nm technology library, exploring its integration with modern ASIC design flows, parasitic extraction, and advanced timing analysis

• Ongoing Self-Study: Enhancing expertise in ASIC design, physical verification, and low-power optimization through self- directed research

• Course work in Digital ASIC Design, VLSI Circuit Design, Analog IC Design, Machine Learning, Embedded Systems, Digital IC Design, Analog & Digital Communication

President, National Social Service Cell (Bachelors) Aug 2019 - Sep 2021

• led strategic planning and execution for 10+ community events, managing and mentoring over 100 members to enhance engagement, streamline operations, and drive impactful social initiatives.

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