Design Engineer Medium Voltage

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David Hong

**** *. ********* **., *******, AZ 85048

Phone: (mobile) 480-***-****

Email: ******.****@*****.***

Work Experience

Renesas Electronics, Principal Device Design Engineer… Tempe, AZ, 2021 ~ 2025

• Developed 2 generations of low~medium voltage Split Gate Trench (SGT) Power MOSFETs for industrial/automotive applications and developing a new generation of SGT Power MOSFET technology.

• Set up TCAD-to-SPICE work flow for SGT MOSFET generations.

• Identified degradation mechanisms SGT MOSFET switches and formulated solutions for the performance and reliability issues unique to SGT MOSFET technologies.

• Established high efficiency design flow & tools to shorten and streamline development cycle and ensure higher quality products.

Atomera, Principal Device Integration Engineer … Phoenix, AZ. 2020 ~ 2021

• Developed novel power MOSFET switches based on OI-layer technology.

• Optimized the device architecture and process conditions for hot carrier injection and SOA. Microchip/Microsemi, MTS, Device Design Engineer …. Chandler, AZ., 2016 ~ 2020

• Developed medium to high voltage SiC MOSFETs (700V~3300V) for industrial and automotive applications complying with JEDEC/AEC standards.

• Developed medium voltage (100V~250V) radiation-hardened MOSFETs for aerospace applications complying with MIL specs.

• Developed low to medium voltage (25~100V) Trench Gate Power MOSFETs for automotive and industrial applications.

• Designed compact high voltage junction termination extension (JTE) structures for SiC MOSFETs for low leakage operation at high temperatures. Reduced termination junction leakage by 10X using 30% of space compared to the conventional termination schemes.

• Developed and set up wafer level HTGB test methodology for SiC MOSFETs’ gate oxide reliability screening for JEDEC/AEC-compliant parts. NXP/Freescale, MTS, Device Design Engineer Tempe, AZ, 2006 ~ 2016

• Created power devices for low to high-voltage applications using various types of device structures such as LDMOS, NPN, PNP, IGBT, SCR.

• Developed on-chip ESD protection devices using BiCMOS/LDMOS technologies

• Performed TCAD simulations to define/optimize device structures and to investigate failures

• Extensively used DOE in developing power device structures for new technologies.

• Delivered PDK libraries in multiple generations of technologies.

• Supported ESD circuit verification for new products and debugging for ESD failures Georgia Institute of Technology, Graduate research assistant Atlanta, GA, 2000 ~ 2006

• Process impact on device and device/circuit performances

• Device reliability verification at design stage

• Fast determination of dielectric reliability using machine learning technique 2/2

• Developed and characterized a prototype GaN HEMT AMD, Internship Sunnyvale, CA, Summer 2001

• Worked on electrical line-width measurement metrology for nanoscale devices

• Performed research on aberration evaluation methodology for DUV/EUV litho. system Samsung Electronics, Device Engineer Kiheung, Korea, 1993 ~ 1997

• Developed Power MOSFET devices for consumer applications

• Performed process optimization, device characterization, parametric analysis

• Designed test structures and performed wafer level bench test

• Performed design rule margin analysis using TCAD and DOE

• Extensively used SPC tools for tight process control and low defect density processes

• Responsible for identifying low yield issues and fast yield ramp up for high volume manufacturing startups

Skills and Tools

• TCAD simulation: Sentaurus TCAD tool suite

• TCAD-to-SPICE Modeling: Synopsys Mystic, Silvaco Utmost4

• Design of Experiment (DOE) and Statistical Data Analysis: JMP, Python

• Layout Design: Cadence Virtuoso, Calibre Physical Verification tool suite, K-Layout

• Circuit simulation: LT-Spice, Cadence Spectre,

• Device Characterization: Parametric Analyzers (SPA/PDA), Curve Tracers, Oscilloscopes

• Programming: Python, Perl, Tcl, Visual Basic VBA, C++, LabView, Cadence SKILL, Unix/Linux Shell script

Education

Ph.D in Electrical Eng. (minor in Statistics) at Georgia Institute of Technology, Atlanta, GA

• Graduation: Dec. 2006, GPA: 3.86/4.0

• Thesis: Modeling of integrated circuit reliability based on the physical design characteristics M.S in Electrical Engineering at Georgia Institute of Technology, Atlanta, GA

• Graduation: May. 2002, GPA: 3.88/4.0

• Emphasis: Semiconductor device physics and fabrication technology Graduate program in Materials Science and Engineering at Cornell University, Ithaca, NY.

• Aug. 1999 ~ May 2000, GPA: 3.74/4.3 (core GPA: 4.15/4.3) B.S in Metallurgical Engineering at Korea University, Seoul, Korea

• Graduation: Feb. 1991, GPA: 4.12/4.5

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