Electrical Engineering System Design

Tejanand Pattemmunirathnamrose

San Jose, CA-***** ************@*****.*** +1-408-***-**** Linkedin EDUCATION

MS in Electrical Engineering, San Jose State University – San Jose, CA 3.39/4 Aug 2023 – May 2025 Course Work: Advanced Digital System Design and Synthesis, Soc Design & Verification with System Verilog, Logic Verification with UVM, Advanced Computer Architecture.

B.Tech in Electrical and Electronics Engineering, Pondicherry Technical University, IN. 3.2/4 Aug 2014 – June 2018 Course Work: Digital Logic Design, Electronics Devices and Circuits, Digital Signal Processing, Digital Design with Verilog. TECHNICAL SKILLS

Hardware Description Languages: Verilog, System Verilog. Methodology: Universal Verification Methodology (UVM). Verification Skills: Verification Using System Verilog, UVM Based Verification, Randomization, Constraints, Assertions, Functional Coverage, IPC, SV Object-Oriented Programming (OOPS), TLM, Config dB, Reusable testbench Architecture. Design Skills: Digital Logic Design, RTL Design and Synthesis, ASIC Design Flow using Verilog, FIFO, Concepts of Clock domain crossing (CDC), Finite State Machines, Parametrized Design, Pipelining and Timing optimization, Clock Gating, Clock Divider, Static Timing Analysis (STA).

Computer Architecture: MIPS 5-Stage, Cache Concepts, Hazards. Protocols: AXI LITE, APB, AHB, SPI, I2C, UART. Scripting Languages: Python (Regular Expressions) and Basics of C. Tools: Synopsys VCS, Model sim, Xilinx-Vivado. Operating System: Linux, Windows, MacOS ACADEMIC PROJECTS

Verification of Vending Machine UVM

• Designed and implemented a finite state machine (FSM)-based Verilog model of a vending machine, handling coin detection, accumulation, purchase validation, and change return logic.

• Integrated realistic simulation behavior using randomized timing delays to model debounce, mechanical delays, and actuator timing for accurate testbench validation.

• Developed return-coin prioritization logic and subroutine-style state transitions to handle constrained coin availability and robust error handling in transactional sequences.

Verification of Parameterized memory SV

• Designed and verified a configurable synchronous memory module with read, write, and reset functionality, using a transaction-level testbench driven by a mailbox-based generator and driver.

• Ensured correct memory behavior through randomized and directed test sequences, validating data integrity, reset-to-default handling, and exclusive read or write operation enforcement. Design and Verification of AXI 3 for HPC Applications UVM

• Led verification of AXI-based IP blocks using UVM, developed layered testbenches, assertions, checkers, and functional coverage metrics to validate AXI3 and AXI Lite behavior.

• Executed directed and constrained-random test scenarios for AXI interfaces, FFT/IFFT modules, and memory-mapped peripherals.

• Integrated scalable verification environments across multiple design blocks, optimizing test modularity and debug with Synopsys. Verification of 128-Point FFT and IFFT OFDM Communication Systems UVM

• Developed a complete UVM verification environment, incorporating assertions and constrained random testing.

• Designed a reference model for OFDM, ensuring a non-synthesizable implementation for accurate verification.

• Generated random 48-bit data as input to both the reference mode and original DUT, comparing outputs in the scoreboard. Implementation of Image Processing functions on PYNQ FPGA board Verilog

• This project performs convolution-based techniques on a given input image.

• DMA controller receives stream data from the IP and transfers it to external DDR memory through the AXI4 interface.

• Processed image is sent back to memory, sent to external world using interfaces or display controllers. System allows real-time monitoring of processed image through connected display units.

• Collaborated with peers/mentors to design test strategies or review plans. Design and Implementation of a 5-Stage Pipelined MIPS32 Processor Verilog Computer Architecture

• Designed and implemented 5 stages of pipelining for the complete execution of an instruction.

• Implemented the RTL Design of the RISC processor using Verilog HDL on Model-sim. Design and Implementation of Cache Simulator Verilog Computer Architecture

• Engineered an m-way set-associative cache simulator supporting cache configurations of 1, 2, 4, 8, and fully associative.

• Implemented dynamic cache sizes (16, 32, 64, 128 KBs) and variable block sizes (16, 32, 64, 128 bytes) for adaptability to diverse memory requirements, LRU algorithm for evaluating and comparing performance under different scenarios.

• Configurable cache design parameters for comprehensive cache optimization studies, including cache size, set associativity, block/line size, and replacement algorithms.

EXPERIENCE(Software)

Consultant, Capgemini Technology Services India Limited – India Aug 2022 - Jan 2023 Software Engineer – Densy’s Consulting Pvt Ltd. Aug 2018 - Aug 2022

• Gained foundational industry experience in Agile environments, version control, and RESTful service integration, with exposure to C++ in backend component development.

• Applied structured unit testing methodologies (JUnit) and collaborated cross-functionally—skills transferable to disciplined hardware and verification workflows.

• This experience provided a strong foundation in structured development, now redirected toward digital design and verification.

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