C++ Digital Design

Taruni Sanjay

+1-301-***-**** ****.********@*****.*** https://www.linkedin.com/in/taruni-sanjay-203812190/ EDUCATION

University of Maryland College Park M.Eng Electrical and Computer Engineering GPA- 3.75/4.0 Aug 2021-May 2023

• Coursework: Modern Digital Design, Microprocessor Based Design, Analog and Digital Communication Systems Vellore Institute of Technology B.Tech Electronics and Communication GPA- 8.55/10 Aug 2016-May 2020

• Coursework: Computer Architecture, VLSI Design, Digital System Design using Verilog, Microcontrollers and its Applications. TECHNICAL SKILLS

Programming languages/tools: System Verilog, Verilog, Universal Verification Methodology (UVM), C/C++, Python, Bash, Git, Tcl Simulation Tools: QuestaSim, Synopsys DVE, Cadence Simvision, Xilinx Vivado, Spyglass, Modelsim, Cadence Virtuoso, Cadence Incisive. Protocols and Documentation Tools: Ethernet (IEEE 802.3), AXI, APB, Pandoc, Latex WORK EXPERIENCE

CoMira Solutions Inc., Design Verification Engineer July 2023-Present

• Created RTL design for a chiplet’s adapter that communicates between the Die-to-Die(D2D) interface layer and the Protocol layer for the Universal Chiplet Interconnect Express (UCIe), supporting data rates from 4GT/s to 32GT/s using the Flit aware Die-to-Die Interface’s (FDI) state machine’s signals.

• Verified a controller module handling the Die-to-Die layer’s datapath using assertions and checkers, guaranteeing better RTL quality.

• Experience with pre-silicon verification of FPGA high-speed interfaces at SoC and IP levels, ensuring alignment with performance and timing constraints and monitoring design and testplan flow including simulation, synthesis, static timing analysis.

• Developed and executed a modular SystemVerilog testbench for the Forward Error Correction PHY design block in compliance with the Ethernet (IEEE 802.3) IP level subsystem, focusing on 200Gb/s lane signaling.

• Achieved 100% state machine, branch, code, and functional coverage for designs, w i t h 98% toggle coverage from

• 200GBASE-R to 1600GBASE-R physical layer implementations at frequencies 800MHz and 1600MHz.

• Debugged, developed, and code-reviewed 20+ bring-up test cases, emphasizing error injection and bypass test cases to validate design integrity through directed and constrained random testing.

• Built and optimized test cases targeting high-speed, low latency of the Ethernet PHY sublayer, implementing cover groups to measure functional and code coverage in compliance with Ethernet standards using UVM. Hughes Network Systems, Hardware Engineering Intern May 2022-Aug 2022

• Performed verification of the LDPC(Low-Density Parity Check) decoder for a hardware accelerator compatible with DVBS2 and DVBS2-X standards eliminate all pipeline collisions due to the 8-clock delay and enhance Clock Domain Crossing logic.

• Initiated verification process using the BAS (Bit Accurate Simulator) decoder, analyzing the system to check and validate both the minimum Frame Error Rate (FER) and Bit Error Rate (BER) for optimal performance.

• Analyzed performance of frames up to 1.00E+06 and checked for best signal-to-noise ratio(SNR) values for 1 bad frame.

• Generated a 64-bit microcode table for fixed and variable edge rates, conducting thorough debugging to ensure accuracy and alignment with channel addresses for precise functionality. Bharat Electronics Limited(BEL), Design Engineer Intern June 2020-Aug 2020

• Devised the block diagram of a BITE algorithm that involves a 4005(Xilinx) FPGA and 8051 microcontrollers.

• Designed the serial interface between both blocks with the help of the RS-422 converter and RS-232 with serial interface mode. TECHNICAL PROJECTS

Polynomial Evaluation Accelerator Verilog HDL, Linux, Git,Xilinx Vivado,Tcl

• Implemented a hardware accelerator with high performance and reduced latency, comprising two input FIFOs (First In First Out) of 16 bits width each and two output FIFOs of 32 bits width each.

• Reconstructed three levels of FSMs (Finite State Machine) along with a RAM controller to manage token consumption and compute polynomial leading to Idle state, firing start, and firing wait state modes.

• Created test benches and netlist files for all sub-modules and established timing summary and power reports for the pareto design.

• Drafted alternative designs which led to a reduction of the number of state modes and equally high efficiency. Histogram Generator Implementation Verilog HDL, C, Unix, Gitlab

• Tested an actor and graph design implementation of the histogram generator used for object tracking, wherein the actor reads pixels of an image from an input edge and exports the bin count of the generator to the output edge.

• Generated the driver executable file using the CMake files and CMake cache files with the help of the lightweight dataflow package and FIFO source and sink codes.

• Formulated the graph design of a window computation actor which invoked a top-level state machine and two lower levels of the FSM consisting of three states to consume tokens from input ports and store the results in the output port to calculate the sum, maximum, and minimum result of the tokens.

• Constructed the graph flow design, and achieved a successful operation cycle for the idle, firing start, and wait stages in Verilog. Simulation, Synthesis, and Testing for a Cyclic Computational Unit Verilog HDL, Xilinx Vivado, Unix, Tcl

• Designed a Mealy FSM’s control unit by designing and implementing a state transition table for three consecutive states, while simultaneously constructing an optimized datapath that included a 2-bit up counter, a 2:1 multiplier, and a 2-bit adder, all of which efficiently computed the carryout for precise control flow and operation.

• Performed logic synthesis and post-synthesis simulation the cyclic unit by executing Tcl script files for each of the modules and ultimately producing netlist files for Artix-7 FPGA.

• Validated test benches and associated unit tests to exercise the unit through simulation.

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