Linux, Python, C, C++, Automation, Hardware integration and bring-up.

Shashank Shivakumar Muthkur

Tempe, AZ +1-623-***-**** ********@***.*** https://www.linkedin.com/in/shashank-s-muthkur/ EDUCATION

Master of Science, Computer Engineering (Electrical Engineering) [August 2024 - May 2026] Arizona State University – Tempe, AZ, USA

Relevant Coursework: Digital System and Circuits, Computer Architecture II, Digital Verification & Testing, VLSI, Fundamentals of Semiconductor Packaging.

Bachelor of Engineering, Electronics and Communications Engineering [August 2018 – July 2022] Visvesvaraya Technological University – Ballari, KA, India Relevant Coursework: Digital System Design, VLSI Design, Computer Organization and Architecture, Microcontroller Architecture, Digital Signal Processing, Computer Networks, Verilog HDL, Embedded Systems. TECHNICAL SKILLS

Programming Languages: C, C++, Python, Verilog.

Tools: Gem 5 Simulator, Cadence (Virtuoso, Layout Suite), Arduino, SBCs, DediProg, KiCAD, Docker, Automation Frameworks, CPU-Z, RWE, Diskpart, Quartus Prime, ModelSim, JIRA, Oscilloscopes and Logic Analyzers. Skills: Automation, Server Board Bring-up, Debugging tools, Advanced Computer Architecture, JTAG, Paramiko (SSH - automation), Pexpect, SystemVerilog for Digital Verification and Testing, Communication Protocols, Linux. WORK EXPERIENCE

Post-Silicon Validation Engineer Intel Corporation (Contingent Worker) [May 2022 – June 2024] Deputed to Intel through Tessolve Semiconductors and Univision Technology Consulting Pvt Ltd, Bengaluru, India Project: Cloud Engineering Fleet Services, DCAI, BDC – Intel

Examined Post-Si Functional Validation of Memory, validated across different DRAM protocols [DDR5, DDR4] on targeted server platforms for Server SoC, demonstrated initial debugging capabilities in validation processes.

Explored cross-platform server validation using Docker and Genie benchmarking tools, validated and automated dynamic access of registers through Python for debugging, and developed scripts which seamlessly integrated with the automation frameworks.

Transitioned from manual validation to automation by developing Python programs for automation frameworks which improved efficiency in debugging, including an error signature extraction program that mapped test line failures for streamlined L1 debug.

Utilized specialized Intel proprietary validation tools to perform microcode updates for SUTs at both the OS and firmware levels.

Validated DDR5 DIMMs with RCD and participated in the 32Gb technology validation of DDR5 Server DIMMs. Familiar with Intel Resource Director Technology (RDT) concepts.

Project: Nex Edge Computing, BDC – Intel

Performed Xeon Gen 4 Server Board bring-up, including flashing and configuring BIOS, BMC, and CPLD, along with debugging.

Executed Memory IP manual validation on platform-specific OS and test content specific such as Debian, CentOS, and RHEL, while conducting initial debugging of test contents.

Gained good technical knowledge of server board peripherals. Acquired extensive experience with UEFI BIOS settings and Grub. ACADEMIC EXPERIENCE

Custom G-Share Branch Predictor Gem5 Simulator Computer Architecture C++ Fall 2024

Designed and implemented a custom g-share branch predictor and ran the benchmark to analyze the working of branch prediction. Branch History and branch Address were 8 bits each and bitwise AND configuration. Developed functionality in C++ for key components, including lookup, update, and management of prediction tables, contributing to a deeper understanding of BP. Cache Replacement Policy Implementation Gem5 Simulator Computer Arcchitecture C++ Fall 2024

Implemented a custom LRU_Variation cache replacement policy in the gem5 simulator, utilizing a specific Insertion and Promotion vector configuration to manage block promotion and eviction. Modified key functions (reset, touch, invalidate, getVictim) and integrated the policy into the gem5 framework by updating source code, build scripts, and configuration files. Design and implementation of 4-bit Adders and Standard Cells SAED 32 nm Cadence Virtuoso Fall 2024

Designed the schematic at the transistor level for 4-bit adder using mirror adder structure. Calculated the worst-case delay, average power, and total layout area of the adder. Designed layout of 4-bit adder by combining 1-bit adders and inverters in layout and

Performed DRC and LVS check for the adders and verified the designs. Driver Drowsiness Detection System RPI 4B RPI CM4 Spring 2022

Monitored driver’s eye blink patterns to alert for drowsiness. Designed a two-layered carrier PCB for Raspberry Pi Compute Module 4 and implemented an OpenCV-Python program to generate EAR scores using a NOIR camera. Secured INR 2.3 Lakhs funding from KTech, NAIN, under the Department of IT, Karnataka, for this innovative project. Led a team of four to develop the working prototype.

Hardware: Raspberry Pi Compute Module 4, Custom Carrier IO board, infrared illuminators, NOIR RPI Camera V2, RPI display, buzzer.

Software: OpenCV-Python, KiCAD, Raspbian 64-Bit OS. Auto Parking Retrieve Assist and Obstacle Avoidance using Arduino Uno IoT Spring 2020

This system automates the retrieval of car from complex parking scenarios while also avoiding any obstacles in real time. The system records the commands given by the user while parking the car, it then reverses its order and retrieves back from parking lot.

Hardware used: Arduino Uno, Car kit, Ultrasonic sensor, HC 05 Bluetooth transceiver and batteries.

Software used: Developed a custom APRA app using MIT App Inventor to control and program the system using Arduino IDE. CERTIFICATIONS AND TRAININGS

Verilog HDL Fundamentals for Digital Design and Verification – Udemy [ongoing]

Programming with Python – Internshala trainings [completed]

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