Design Engineer Physical

Bhargav Kancharla

*************@*****.*** +1-954-***-**** LinkedIn

Professional Summary:

Physical Design Engineer with over 5 years of experience in ASIC and SoC design across advanced technology nodes (5nm, 7nm, 10nm, and 14nm). Expertise in block-level physical design, place & route (PnR), clock tree synthesis (CTS), timing closure, IR drop, and EM analysis. Proficient in EDA tools like Synopsys ICC2, Cadence Innovus, PrimeTime STA, ANSYS RedHawk, and Mentor Graphics Calibre for design implementation, verification, and sign-off. Strong background in timing and power optimization, signal integrity, multi-corner multi-mode (MCMM) optimization, and RTL debugging. Skilled in TCL, and Shell scripting for workflow automation and CAD flow enhancements. Experience in high-performance computing, mobile processors, AI accelerators, and GPU designs, contributing to first-pass silicon success and successful tape-outs.

Technical Skills:

Physical Design Tools: Synopsys Fusion Compiler, ICC2, Cadence Innovus

Timing & Power Optimization: Static Timing Analysis (STA), IR Drop & EM Analysis, Power Grid Optimization.

EDA Tools: Synopsys ICC2, Cadence Innovus, PrimeTime STA, ANSYS RedHawk, Mentor Graphics Calibre.

Signoff & Verification: DRC/LVS Checks, LEC, EMIR, timing closure

Scripting & Automation: TCL and Shell.

Cross-Functional Collaboration: DFT Integration, RTL Debugging, Final Tape-Out Readiness.

Professional Experience:

Physical Design Engineer Jan 2024 – Present

SkyWater Technology – Kissimmee, Florida, USA

Project Name: Advanced 5nm ASIC Design for Custom Semiconductor Solutions

Led block-level physical design activities, including floor planning, placement, clock tree synthesis (CTS), routing, and timing closure for custom ASICs.

Worked on 5nm technology node for high-reliability and radiation-hardened semiconductor applications.

Optimized CTS to enhance signal integrity, reducing skew and latency for high-performance applications.

Debugged timing violations using PrimeTime STA, optimizing setup, hold, and transition timing to meet stringent design specifications.

Performed IR drop and EM analysis, implementing fixes to ensure power integrity and long-term reliability.

Worked on PNR and timing closure aspects (Place and Route) for high-frequency, performance-intensive IPs, analyzing congestion, module/memory placement, IR drop, and clock quality to achieve optimal design closure.

Successfully taped out multiple blocks with a gate count of 2 - 3 million, meeting delivery timelines.

Analyzed PPA trends, performing sweeps across multiple parameters to devise strategies for achieving the best performance, power, and area trade-offs.

Collaborated with cross-functional teams (RTL, DFT, CAD, and verification) to resolve design issues and ensure efficient design convergence.

Physical Design Engineer Jan 2019 – Feb 2023

Capgemini – Bangalore, India

Project 1: Meteor Lake (MTL) – Intel

Developed and optimized block-level physical design, ensuring efficient floor planning, placement, CTS, routing, and timing closure using Synopsys ICC2.

Debugged timing violations and optimized data paths, applied timing ECOs using Synopsys PrimeTime to achieve final timing closure.

Resolved IR drop and EM violations using ANSYS RedHawk, ensuring robust power integrity at advanced nodes.

Conducted DRC and LVS verification using Mentor Graphics Calibre, ensuring foundry compliance.

Automated design workflows using Perl and Tcl scripting, improving efficiency and reducing manual effort.

Worked closely with CAD teams to identify and report flow issues, contributing to continuous tool improvements.

Project 2: Snapdragon 8 Gen 2 – Qualcomm

Performed block- and chip-level floorplanning and placement for a high-performance mobile processor.

Optimized CTS to achieve low power and minimal skew using Cadence Innovus.

Addressed signal integrity issues by implementing shielding, spacing, and layer optimization techniques.

Conducted power analysis and optimization to reduce leakage and dynamic power consumption using ANSYS RedHawk.

Ensured sign-off convergence by performing STA, electrical checks, and physical verification.

Played a role in enhancing CAD flow by identifying and reporting issues, leading to improved tool versions.

Project 3: MI300 GPU – AMD

Designed and optimized high-speed data paths for a next-generation AI and gaming GPU.

Optimized power grid distribution and decap placement, reducing IR drop and power noise.

Performed final sign-off verification, including IR/EM analysis, DRC, and LVS closure, ensuring successful tape-out readiness.

Worked closely with RTL designers and verification teams to debug and resolve physical design issues.

Automated reporting and debugging processes using Shell scripting, improving design cycle efficiency.

Handled multi-voltage blocks with multiple power domains and implemented UPF strategies for low-power designs.

Ensured LEC and low-power verification (VCLP) were clean, contributing to first-pass silicon success.

Education

Master of Science, Information Technology & Project Management at Indiana Wesleyan University, Merrillville, IN, USA

Bachelor of Technology, Electronics & Communication Engineering at Priyadarshini Institute of Technology & Management, Guntur, AP, India

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