Hardware Security Computer Engineering

Zhaokun Han

+1-979-***-**** ********@*****.*** www.linkedin.com/in/zhaokun-han/ College Station, Texas 77840 Education

Texas A&M University (TAMU) College Station, Texas Ph.D. degree in Computer Engineering, majored in hardware security, GPA of 3.87/4.0 Sep. 2018 – Dec. 2024 University of Science and Technology of China Hefei, China B.S. degree in Physics, GPA of 3.6/4.3 Sep. 2014 – Jun. 2018 University of Western Australia Perth, Australia

International Research Training Program in Electrical, Electronic and Computer Engineering department Jun. 2017 – Aug. 2017 Work Experience

ASIC Integration Engineer Graduate Intern San Jose, California Internship at Intel Corporation May 2022 – Aug. 2022 Job Content: Tested and enhanced a library parser on Intel eASIC platform, and evaluated a hardware security countermeasure on eASIC. Ph.D. Student Researcher ECE at TAMU

Collaboration with Intel in Structured Array Hardware for Automatically Realized Applications (SAHARA) program Dec. 2020 – Dec. 2023 Job Content: Built and developed a hardware security countermeasure to defend against intellectual property (IP) piracy on the eASIC platform. Research Assistant (RA) & Teaching Assistant (TA) ECE at TAMU Secure and Trustworthy Hardware (SETH) Lab Sep. 2018 – Dec. 2024 RA Job Content: Developed secure IP protection techniques and evaluated/assessed security of existing IP protections in hardware security. TA Job Content: Mentored student class projects in the course “Security of Embedded Systems (ECEN426/489/759)” for seven semesters. Technical Skills

Programming Python, Verilog, C, MATLAB, Mathematica Tools Synopsys (Design Complier, Formality), Cadence (Genus, Conformal LEC), Siemens EDA/Mentor Graphics (Precision RTL Synthesis, ModelSim), Xilinx (Vivado), Academic Tools (Berkeley ABC, Yosys, Verilator) Languages English (professional), Mandarin (native) Courses

Analysis of Algorithm Digital Integrated Circuit Design Theory of Computability Theory of Probability Quantum & Logic Synthesis Introduction of VLSI Design Automation Principles of Deep Learning VLSI Systems Design Microprocessor Systems Design Reinforcement Learning Advanced Computer Architecture Secure Authentication Research Experience

FuncTeller: A Heuristic Attack to Retrieve Design Protected by Embedded FPGA (eFPGA) ECE at TAMU Involved skills: Python, C, Verilog, Design Compiler, Genus, Innovus, Formality, Conformal LEC Dec. 2021 – Jun. 2023 Content: Evaluated security of eFPGA-based redaction and proposed an attack recovering circuit functionality with only black-box query access. Sparse Prime Implicant Attack on SFLL-fault Technique ECE at TAMU Involved skills: Python, C, Verilog, Design Compiler, Genus, Precision RTL Synthesis, Vivado Apr. 2019 – Jan. 2021 Content: Analyzed the security of a state-of-the-art and unbroken logic locking technique and proposed an attack to break the technique. Hiding Instructions on Processors ECE at TAMU

Involved skills: Python, Verilog, Design Compiler, ModelSim May 2020 – Oct. 2020 Content: Designed and developed two locking schemes on processors with hidden instructions in both performance and security perspectives. SCONE: Efficient Hardware IP Protection Utilizing SMT Solver and Circuit Encoding Scheme. ECE at TAMU Involved skills: Python, Verilog, Design Compiler Aug. 2023 – Nov. 2024 Content: Proposed a secure and efficient logic locking technique while addressing research challenges in scalability, flexibility, and security. STATION: State Encoding-Based Attack-Resilient Obfuscation ECE at TAMU Involved skills: Python, Verilog, Design Compiler May 2022 – May 2024 Content: Proposed a secure encoding scheme for a novel sequential obfuscation technique against existing attacks of logic locking. BAT: Boolean Algebraic Transformation to Protect Hardware IP on Intel eASIC Platform ECE at TAMU Involved skills: Python, C, Verilog, Design Compiler Dec. 2020 – Dec. 2023 Content: Developed secure and efficient locking technique on the Intel eASIC platform with Intel and other universities in SAHARA program. Cybersecurity Awareness Worldwide (CSAW) Competition 2021 ECE at TAMU Involved skills: Python, Verilog, Design Compiler, Berkeley ABC, Verilator Sep. 2021 – Nov. 2021 Content: Led a team with other two postdocs to hack the competition circuits redacted by eFPGA and achieved the 1st place winner. CSAW Logic Locking Competition 2019 ECE at TAMU

Involved skills: Python, C, Verilog Sep. 2019 – Jan. 2020 Content: Led a 3-member team participant in the hacker competition aiming to break the state-of-the-art unbroken locking technique. Multi-Objective Strategies for SFLL ECE at TAMU

Involved skills: Python, C, Verilog, Design Compiler Dec. 2018 – Nov. 2019 Content: Proposed three metrics to achieve a better trade-off between security and output error rate of a state-of-the-art logic locking technique. Publications

[1] Zhaokun Han, D. Xing, K. Amberiadis, A. Srivastava, and J. Rajendran, “SCONE: A Logic Locking Technique Utilizing SMT Solver and Circuit Encoding Scheme for Efficient Hardware IP Protection.” Accepted in ACM/IEEE Design Automation Conference, 2025.

[2] Zhaokun Han, A. Dixit, S. Patnaik, and J. Rajendran, “STATION: State Encoding-based Attack-Resilient Sequential Obfuscation.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024.

[3] Zhaokun Han, M. Shayan, A. Dixit, M. Shihab, Y. Makris, and J. Rajendran, “FuncTeller: How Well Does eFPGA Hide Functionality?” USENIX Security Symposium, 2023.

[4] Zhaokun Han, A. Dixit, S. Patnaik, K. Amberiadis, and J. Rajendran, “BAT: Boolean Algebraic Transformation on eASIC.” Government Microcircuit Applications & Critical Technology Conference, 2023.

[5] Zhaokun Han, M. Yasin, and J. Rajendran, “Does logic locking work with EDA tools?” USENIX Security Symposium, 2021.

[6] B. Tan, R. Karri, N. Limaye, A. Sengupta, O. Sinanoglu, M. Rahman, S. Bhunia, D. Duvalsaint, R. Blanton, A. Rezaei, Y. Shen Y, H. Zhou, L. Li, A. Orailoglu, Zhaokun Han, A. Benedetti, L. Brignone, M. Yasin, J. Rajendran, M. Zuzak, A. Srivastava, U. Guin, C. Karfa, and K. Basu, “Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.” ArXiv preprint arXiv:2006.06806, 2020.

[7] Zhaokun Han, L. Brignone, A. Benedetti, M. Yasin, and J. Rajendran, “Protecting IC Supply Chain through Stripped-Functionality Logic Locking.” Government Microcircuit Applications & Critical Technology Conference, 2020.

[8] Zhaokun Han, M. Yasin, and J. Rajendran, “Multi-Objective Strategies for Stripped-Functionality Logic Locking.” IEEE International Symposium on Circuits and Systems, 2020.

[9] F. Foroozandeh, J. Wang, R. K. Nachimuthu, Zhaokun Han, D. Johnson, S. Fontenot, B. Nener, G. Parish, and M. Myers, “Nitrate ion detection using GaN/AlGaN/GaN-based reference-electrode-free sensors with tripodal receptor functionalisation.” Australian Institute of Physics Congress, 2018.

[10] N. Yang, Zhaokun Han, M. Tian, K. Zhao, Z. Zhang, and X. Tao. “Information transmission and re-read by acousto-optic effect.” Physics Experimentation, 2017.

Awards, Honors, and Leaderships

Leadership Led to Organize Global Hardware Security Competition HeLLO CTF 2023 2023 Top Picks Top Picks in Hardware and Embedded Security Workshop 2023 for USENIX’21 Publication 2023 Leadership Led a Technical Team for Providing Challenge Designs and Performance Evaluation in HeLLO CTF 2022 & 2023 Competition 1st Place in Cybersecurity Awareness Worldwide (CSAW) Global Competition 2021 Travel Grant Student Travel Grant in IEEE International Symposium on Circuits and Systems and USENIX Security 2020 & 2023 Competition Finalist in CSAW Global Competition 2019 Scholarship One-time Departmental Scholarship in ECE at TAMU 2018

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