Physical Design, RTL Design in Verilog, Python and TCL Scripting

Sarika Jothi Alwarappan

480-***-**** • ****************@*****.*** • https://www.linkedin.com/in/sarikaja/ Education

M.S Computer Engineering (Electrical Engineering) Arizona State University May 2025 Coursework- Hardware Security and Trust, VLSI Design, Digital Systems and Circuits, CGPA: 3.4 Computer Architecture, Analog Integrated Circuits, Reconfigurable Computing. B. Tech Electronics & Communication Engineering SASTRA university, Thanjavur, India May 2023 Coursework- Embedded & Signal processing architectures, Microprocessor & Microcontroller, Real time operating systems. CGPA:3.2 Skills

Programming languages: C++, Python, Verilog, SystemVerilog, TCL. Tools: Gem5, Virtuoso, Caliber, Innovus, Design Compiler, StarRC, Hspice, Quartus, Questa Sim, Vivado, Vitis HLS, ADS, Ansys. Professional Experiences

Graduate Service Assistant August 2024 –Present

• Graded for CSE 320: Design/Synthesis of Digital Hardware, evaluating homework, lab work, and demos for 84 students.

• Reinforced my foundational knowledge in Digital Design by analyzing student solutions, providing constructive feedback. Internship: Collins Aerospace (RTX-Raytheon Technologies Corporation), Hyderabad, India February -June 2023

• Created system icons for avionics applications, learnt shell programming and python scripting for automating system processes.

• Programmed LimeSDR using LimeSuite in a Linux environment, learning in detail about GNU Radio technologies. In plant training: Bharat Sanchar Nigam Limited (BSNL-Indian telecom corporation), India February 2022

• Obtained hands-on experience with telecom networking and testing equipment like node B, E node, BTS, OFC systems

• Acquired broad insights into the telecom infrastructure, 2G, 3G, 4G, 5G networks, working with telex and optical fiber connectivity. Academic Projects

Spring 2024

ASIC Design- RTL to GDSII of a GCN (Graph Convolutional Network) (Power – 6.34 mW, Leakage -0.0207%, Latency- 135ns)

• Designed and implemented the GCN module using RTL Design, followed by functional verification and logic synthesis to generate an optimized netlist.

• Performed Floorplanning, Automated place & route (PnR), and Clock tree synthesis (CTS) using Cadence Innovus and TCL scripting, ensuring timing closure and area optimization.

• Conducted post-layout correction and optimization, refining power and performance metrics while maintaining design integrity.

• Achieved clean LVS and DRC signoff, finalizing the GDSII layout. Spring 2025

Secure Hardware ID Generation using Custom Arbiter PUF in Verilog

• Designed and verified Arbiter and Ring Oscillator PUF architectures in Verilog, utilizing race conditions and process variation modeling to generate unique 32-bit and 4-bit hardware response signatures, respectively.

• Simulated and harvested 300+ CRPs across 16 PUF instances, evaluated entropy via Single- and Multi-Chip Hamming Distances.

• Synthesized RO PUF on Cyclone V FPGA using Quartus; applied TCL-based placement of 64 ROs for minimal skew and consistent behavior.

Spring 2024

Digital Design- Pipelined and Shared Model of Taylor Series in Arria 10 FPGA

• Developed RTL Design for a 5-stage pipelined and shared operator architectures of function circuit, verifying with QuestaSim.

• Synthesized, and visualized the design after Place & Route using Quartus Prime, comparing throughput, power, and area tradeoffs, optimizing latency and resource utilization.

Spring 2024

Digital Design - Gemm Accelerator for a PYNQ-Z2 SoC-FPGA using High Level Synthesis

• Designed a 16x16 GEMM accelerator in C++, generating HDL, synthesizing and performing Place & Route using Vitis HLS.

• Optimized Unrolling, Pipelining and Array Partitioning variations on the tool, improving latency resource usage and execution speed.

• Analyzed FPGA resource utilization (BRAM, DSP, LUTs) for better power-performance trade-offs in real-time acceleration using Vivado. Spring 2024

Digital Cell Design and Verification for OAI_33(Or_And_Invert) using 7nm PDK

• Designed OAI_33 cell schematic and layout in Virtuoso (7nm PDK, FinFET) ensuring efficient transistor placement.

• Performed DRC/LVS verification, creating a 3x3 array layout for multi-cell integration.

• Conducted post-layout simulations in StarRC, optimizing power, area, delay for improved performance.

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