Software Engineer C++

Frank Perron

Palo Alto, CA

Objective:

As a Sr. Signal and Image Processing Engineer/ Principal Software Engineer, and team builder, I have provided strong, experienced leadership to many dynamic organizations. Your opportunities will utilize my skills and experience building solutions that you require – on time and on budget. As a role model, team mentoring, and leadership responsibility are welcome.

Experience:

I bring to the table over 10 years with Visual Studio development environment including: C, C++, C#, F#. More than 10 years Assembler for Intel-x86, PowerPC, TI and Motorola Digital Signal Processing (DSP) chips for DSP processing. I built on MATLAB / SIMULINK and that runs in a heterogeneous environment. The tools used included: CUDA library from NVIDIA, MATLAB, C++, Python. I have worked with both RISC-V and MIPS Instructions Set Simulator (ISS). I have Deep Hardware understanding of this GPU HW-design and the OpenGL & OpenCL library code. I have direct hands-on experience with numerous application domains:

• Pre-Silicon EDA tools for GPU design verification–Qualcomm & Samsung GPU and Mobile Wireless embedded System Software – Android, Qualcomm. Linux/Android Native C++ drivers and Java Application development - Qualcomm HW GPU pre-Silicon testing with Mentor Graphics Veloce emulation systems.

• LLVM compiler tool chain - VolantisSemi

• Aerospace- Guidance Navigation and Control, CSDL, Raytheon

• Ion Mobility Spectrometry, Portals for Bomb detection, Implant Sciences Corp Computer Graphics-Virtual Reality infrared scene rendering Gaertner.

• Radar, Digital Beam Forming, track merging, Applied Radar & MIT/ LL

• TCP/IP to 10-Gbps embedded control, Avaya

• Hyper-spectral, Visible, and Infrared, Bodkin

• Real-time Video Capture, uncompressed, Joslin Diabetes

• Medical Voxel Rendering–Visualization of volume datasets. Joslin Diabetes Accomplishments:

As a hands-on development leader with deep software & hardware experience, I know how to:

• Design and document a proposed solution.

• Organize the systematic development of the solution.

• 1) Unit test; 2) Integrate and test; 3) Deploy and test the solution. Utilize embedded software/ hardware development tools:

• New device drivers for ARM-Linux & x64Windows (7, and 10)

• Signal Generators, RF and Microwave.

• Avaya, Applied Radar FPGA design tool s and simulators.,

• Applied Radar, Avaya.

• CUDA Nvidia & MATLAB many projects.

Software Experience:

• Tools– every modern environment including:

o Over 15 years using C, and 11 years using C++. o 8 years using C#, along with XML and MS-SQL, all now with Visual Studio 2005 to 2019. o 4 major projects using DSP embedded development, and Board Support Packages, o Tools used: Azure, WPF, C#, C++, Perl, Python,

o Lex (Flex), Yacc (Bison) and modern LLVM tools

o Real-Time OS (RTOS), Linux/ Android, pSOS, WindRiver, etc. o Compiler development – pre LLVM (Flex-Bison) and with LLVM tool chain o 10 years with Linux development environments.

• Graphics OpenGL and Raytracing o 10 years with Visual Studio development environment including: C, C++, C#, F# o 10 years Assembler for Intel-x86, PowerPC, TI and Motorola Digital Signal Processing (DSP) chips for DSP processing of images, audio and video signals.

o 10 years, Mathematica & MATLAB/ SIMULINK design tools. o 1 + year with Altera & Xilinx: FPGA Design Language and VHDL. o 20 + years with tools like: All Windows-XP, UNIX / Solaris / Linux and DOS tools, make, VI, LEX, YACC, Tcl/Tk, LLVM, Perl, OpenGL, etc. o Significant project experience developing algorithms for Radar signal processing, Image processing and compression. Hardware Experience:

• Modern NVIDIA GPU designs, pre-Silicon (Blackwell) and NVIDIA Volta-Ampere-Hopper (2020-2022)

• Modern GPU designs, pre-Silicon; Samsung (2015-2019)

• Modern GPU designs, pre-Silicon; Qualcomm (2011-2015)

• Numerous applications using Embedded DSP Single Board Computers, running Linux, pSOS, WindRiver OS, or other RTOS. Four major projects using TI hardware.

• DSP FPGA based designs using multiple Altera Stratix parts Work Experience:

02/24 to 11/24

VolantisSemi, CA

(Stealth–Angel funded)

Sr. Consultant–Architect for HW & SW code sign- preSi. Designing HW and SW stack to address high Volume LLM inference market.

• Role: Leadership role, Consulting LLM inference computational flow. Providing System Architecture design and initial prototype solutions.

• Leadership: First consultant to start the SW stack development on RISC-V and vector extensions and also developed FPGA based prototype for tensor core, using BFloat format.

• Developed: LLVM Compiler and data visualization tools are coded in C++ as needed for tools development. o The development of LLVM backend code generation for new instructions that extend the RISC-V ISA. o LLVM code package made production available for daily builds. o Researched LLVM usage in AI code generation for LLM/AI 8/22 to 2/24

Raytheon, Annapolis Junction, MD

Fulltime Employee – Architect & Team Lead,

Sr. Principal Software Engineer

With DoD Secret clearance, investigation Spring 2023

• Role: Highly visible and influential leadership role, consulting on Jaguar, HEaT and other imaging projects. Providing System Architecture guidance and initial prototype solutions.

• Leadership: Quickly started to manage the tasking of a small team of 4+ Sr. Staff SW/ HW Engineers.

• Developed: Debug and data visualization tools, coding in C#, C++ as needed for new projects. o Undertaken 4 major projects using DSP embedded development, Board Support Packages, Real-time OS (RTOS), Linux /Android, pSOS, Wind River, etc.

o Developed extensive simulation tools that I built on MATLAB / SIMULINK and that runs in a heterogeneous environment. The tools used included: CUDA library from NVIDIA, MATLAB, C++, Python, and a MIPS Instructions Set Simulator (ISS).

o Coded CUDA kernel code to parallel execution of DSP algorithms o Experience in Aerospace-Guidance Navigation and Control. o Experience in Custom control of Synopsys, Cadence and Mentor Graphics’ emulation, hardware platforms. o Experience in Control system design, documentation, and troubleshooting. o Radar signal processing and modeling for an airborne ISR platform. Also implemented satellite EO image processing algorithms in C++.

• Research: continued to explore the LLVM tools, for possible radar DSP applications

• Mentoring: new hires and staff needing advanced training. 5/19 to 4/22

NVIDIA, Santa Clara, CA

Fulltime Employee - Architect & Team Lead, Sr. Principal Software Engineer Role: Highly visible and influential leadership role, using CUDA.

• CuDNN library management and new advancement of algorithms (Deep Neural Networks).

• Leading team of developers and interfacing with key ML frameworks: o Tensor-Flow,MXNet,PYTorch,Caffe2 o Deep HW understanding of NVIDIA GPU. o CuDNN, OpenGL & OpenCL library code.

• Leadership: Quickly took over the daily and long-term equipment requirements of a team of 8+ Sr. Staffs including SW /HW Engineers.

• Developed: Kernel code with CUDA (API) to find faults. These are triaged, and root cause debugged. o Develop and Developed: Algorithms (C++, CUDA) to find faults. These are triaged, and root cause debugged. o Develop and integrate our tools into the Machine Learning Frameworks o Developing new tooling to support the visualization of DDN errors and precision changes. o Azure cloud – CI/CD flow, with Docker & Jenkins. o Expertise in Analog/ Mixed- signal/ RF circuit design, interface electronics for MEMS and sensors, system development involving device modeling, analog front ends and digital Signal processing.

• Research: LLVM tools, for extension to CUDA C++ compiler tool chain

• Benefited: ML Framework teams, world-wide user community.

• Experience: Hands-on new ML development from a wide range of application areas. 2/17 to 5/19

Samsung SSI, San Jose, CA

Fulltime Employee– Solution Architect & Team Lead, Sr. Principal Software Engineer.

• Role: Highly visible and influential role Samsung GPU/ CAD design team, HW Emulation Data Mining and Visualization Lead.

o Deep HW understanding of this GPU HW-design and the OpenGL & OpenCL library code. o Low level AOSP development with BSP for Android versions: Android Nougat (7), Oreo (8) Pie (9) Leadership: Quickly formed a team of 6 Sr. Staff SW/ HW Engineers. o Develop and integrate our tools into the pre-Silicon, Emulation Flow o Tooling also supports deep GPU SW debugging of the core and shader pipe.

• Developed: GPU kernel algorithms for debug to find faults, hangs HW errors.

• Developed: Unique data reduction and visualization algorithms (C++) to find incorrectly rendered images. These are automatically processed and triaged. o Rendered Images with Raytracing. o Custom control of Synopsys, Cadence and Mentor Graphics’ emulation, hardware platforms.

• Benefited: HW Architecture team, resulting in quick turn-around of fault-to-resolution in the RTL design flow.

• Experience: Hands-on, full stack development from applications (games & structured tests) to API (OpenCL, OpenCV, OpenGL and Vulkan) to device driver (Windows and Linux) and finally RTL performance data instrumentation, using System Verilog.

• Explored: The retargeting of all future tooling on the Azure Stack cloud platform, on-premises, using FaaS FPGA as a Service.

02/16 to 09/16 Ancera,

Branford, CT

Fulltime Employee–Architect & Team Lead, Sr. Staff Software Engineer.

• Role: Ancera is a startup, developing a desktop instrument for bio-pathogens detection o Productize the Assay Detection Protocols.

• Developed: Desktop unit’s application software, C++, Prototyped the UI using ‘Material Design Style” tooling and Windows UI.

02/11 to 10/15

Qualcomm Technology, Boxborough, MA

Fulltime Employee– Team Lead, Sr. Staff Software Engineer.

• Role: Tasked with building a robust pre-Silicon testing environment for GPU core graphics driver. o ThetestingoftheindustrystandardOpenGLesgraphicslibraryisnowsupportedonMentor Graphics Veloce RTL emulation hardware, coded in System Verilog.

• Leadership: Lead the effort to hire a focused team of 5 Sr. Software engineers. o Built a highly effective group.

• Developed: Data visualization for system failure cases: o These failures were involving complex GPU internal HW state, and the corresponding software data structures. o Coded OpenCL and OpenCV test and performance applications. o OpenCL on the Snapdragon- GPU code was benchmarked and compared to OpenCL and CUDA processing times. o Using C++ & C# and OpenCV, System- Verilog and SQL, targeted ARM pre-production boards. o Using custom BSP and Linux Native C++ development

(driver and application) o Android AOSP- Honeycomb (3), Ice Cream (4), Jelly Bean (4.1), KitKat (4.4)

• Benefited: SW OpenGL & Android driver team received total support, in a rapid response to new feature requests.

• Experience: I fully understand modern GPU hardware designs at the circuit design level, firmware level, device driver level and application programming level. o Tools used: Verilog, C#, C++, Python. o Extended Raytracing tool kits.

• Explored: Re-implemented open-source ray-tracer software from C++ to F#, as proof-of-concept.

• Functioned as technology lead for Power Delivery Network (PDN) and Signal Integrity (SI) within the customer engineering hardware applications team.

05/08 to 02/11

Draper Laboratory, Cambridge, MA.

Fulltime Employee– Member of Technical Staff, Sr. Software Engineer US Navy Ballistic Missile system GNC testing

• Role: Directed the testing coverage of missile guidance flight software. o Architected the approach to cross checking the embedded flight software against the detailed functional test matrix, of 100’s of requirements clauses.

• Leadership: Direct management of a team of off-site subcontract test engineers from General Dynamics. o The off-site team of 5 engineers that needed a strong hand in day-to-day management to stay on track and to better interface with the embedded SW group at Draper working on missile guidance flight software.

• Developed: The software testing infrastructure that utilizes a set of simulation tools built by the missile Simulation Group within Draper Used DO-178; Design Assurance Level – A.

• Benefited: The program office within Draper that was performing system wide V&V was the internal customer.

• Experience: Rapidly came up to speed on the code base, tools, and extensive requirements documentation that the project utilized. o Developed extensive simulation tools that I built on MATLAB /SIMULINK and that runs in a heterogeneous environment.

o The tools used included: CUDA library from NVIDIA, MATLAB, C++, Python, and a MIPS Instructions Set Simulator

(ISS).

• Explored: Provided mentorship to an additional 2 Northeastern University Coop-Op students.

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