Lead Principal Ic Design

Alexander Odishvili

Objective:

Get technical management or Lead Principal IC designer position. Proficient in IC design, pre- silicon circuit design and IC CAD implementation. Have done around 14 Multi-Purpose Wafer Analog SoC tapeouts in BiCMOS and CMOS Including FiNFET 14nm LPP. Expertise in ROIC, RFIC, PMIC, LIDAR. Verilog/RTL HDL design and verification. Tsmc 110nm, Xfab 350nm High Voltage, Nisshimbo 350nm, Magna 350nm

Education:

New Jersey Institute of Technology, Newark, NJ, USA.

MS Electronics Engineering

Tbilisi State University,

BS and MS Radio physics and Electronics

University Project:

CDMA 2GHz Power Amplifier design with ANADIGICS

Internship:

Lucent Technologies

Wrote C numerical optimization function Fitting Software with Matrix Inversion and second derivative method.

Texas Instruments Technical University

UC Berkley advance VLSI interfaces ADC, DAC, Digital, SC and analog Filters, PERL, UNIX, Synopsys DC

Work Experience:

SeeDevice Inc Jan 2024 – Present

Lead quantum CMOS imager designer

Perform Analog design and Analog mixed signal verification: 12 bit ADC design 50Msps

Performed Calibre tool setup, DRC, LVS, PEX. Camera Systems 200nm to 1.5um wavelength

ROIC circuit library design IVC, CDS, SC SandH, PGA, ADC, Row and Column Decoders

Handmade digital design adder and fifo for pipelines adc and mdac.

CMOS Quantum Solar Cell design 4V 20A, design 3kV HBM ESD protection on chip

L3Harris Jan 2021 to Oct 2023

Lead EO iR ROIC designer

Design 8um pitch 8Kx6K IR LWIR ROIC.

Design analog ROIC Library in Skywater 90nm process. Won L3Harris Call for idea competition with proposal 3D DROIC with enhanced performance.

Wrote white paper: ROIC enhancement main 3 directions. Technological guidelines and design initiatives.

Verified in QuestaSim using system RNmodel Verilog/RTL and in Cadence hierarchy editor Verilog and Spectre following ROIC design sub systems: Reset settling and distribution. Vertical row scanner and its programmability.

Timing Control sequencer 60fps Readout. Timing sequencer interaction with column ADC.

Designed Unit pixel cell.

Designed 8um width correlated double sampling ADC 10-bit MSB and 10-bit LSB, overall ENOB=16bit and LSB=1.2mV. used for acoustic signal processing for submarines.

Root cause analysis debugging and troubleshooting several dual mode MWIR/LWIR ROIC post silicon.

Supervise layout designers for ROIC Analog Library bottom-up creation.

Wrote proposal for DARPA satellite imager system. Wrote proposal for NAVY iR imager system. Cadence Excilium System Verilog/RTL modelling of Switched Capacitor third order digital filter and other complex systems. Design high order Switched Capacitor Audio Filter.

Design 8-bit CRYO+MIL programmable voltage source with integrated noise 22nVrms.Layout this programmable Voltage source. Design high linear Digital temperature sensor +/- 3-degree accuracy over

-196C to +80C temperature range. Wrote Linearity data processing program in MATLAB. Supervise senior analog designer in PLL design and simulation.

Alphacore Inc- Phoenix, AZ Nov 2017 to Jul 2020

Principal High Performance Analog SoC designer

Designed Geiger mode pixel area LiDAR and its ROIC in On-Semi 180nm

Designed IR 256X256 pixel two color sensor area READOUT and ROIC in

On-Semi 180nm. Design 20-bit ADC (3.9mV resolution, 3MHz)

Design complete analog Library for Image area ROIC and DROIC.

Design RadHard Digital LDO SoC for NASA.

Design Acoustic piezoelectric MEMS transducer and its 60V driver.

Wrote proposal RadHard 60MHZ Radar system for Army and NAVY

Wrote proposal LiDAR for NAVY Submarine detection.

Design RadHard DC-DC BUCK using eGaN power Transistors to supply WIMAX PA. Driver in ON-Semi 0.35um process.

Design in TSi 180nm process NFC mixed signal SoC with Envelope tracking on supply. Designing 128X128 Geiger Mode Flash LiDAR for MDA in 180nm CMOS. Won Principal Investigator project for high Temperature 32-bit Microcontroller: RISC-V for jet engine distributed control systems design in GF FDX22. Won Principal Investigator project for PAM4 communication for CERN LHC.

Velodyne advance Lidar R&D Lab- Alameda, CA Nov 2016 – Aug 2017

Senior Analog IC and SoC designer

Deign Time of Flight Lidar SoC for self-driving cars

Design programmable 1GHz ring VCO with 10KHz precision.

Design Trans-impedance amplifier, bias and bias distribution.

Clock and clock distribution. Timer and ADC. Trigger systems.

ENCORESEMI- Silicon Valley Jan 2015 to Aug 2016

Senior Analog VLSI SoC Integrate Circuit designer, working for IBM and Global Foundries

Designing 30GB and 56GB DFE RX, CDR phase rotator in Global Foundry-Samsung 14nm FinFET bulk CMOS 14LPP process. Phase Interpolator,

Duty Cycle Correction. Using Synopsys Extraction tools icvLvs/StarRcxt in 14nm FiN fet CMOS14LPP technology. Using Mentor Graphics Extraction Tool Calibre.

Using cadence VerilogAMS with wreal Verilog Ams models for CDR mixed signal design. Using SpectreRF PSS and PNOISE for Random Jitter simulation calculations in CDR. 10Gbps SERDER.

GigOptix- San Jose, CA Sep 2012 – Aug 2014

Senior RFIC designer

Fiber Optics TIA, CTLE/PGA/AGC and Modulator Drivers 28GHz. 4 channel SoC

PA, frequency doubler and quadrupler, attenuators, VCO, PLL, divider, modulator. RSSI, QAM64 signal Envelope Detector. Design couplers, combiners for E-Band. Using IBM HBT Sige8hp 120nm process in cadence icfb6.1.5, ASSURA401.71GHz-76GHz, 81GHz-86GHz.LVDS driver, 20GHz VCO.

SiTune corporation- San Jose, CA Oct 2011 – Apr 2012

Senior RFIC designer

Design and redesign satellite TV 65nm CMOS receiver front: LNA, LC stages, VGA, PGA, Impassive mixer, RF RSSI and BB RSSI, BB filter, opamp. ET for OFDM DVB-S2.

Transferred and verified multi-standard low-IF Tuner from CMOS charter 130nm process to RF CMOS tsmc 65 nm process.

Satellite tuner evaluation: CNR, DR with phase noise, intermodulation with AWGN, Accusing Rohde & Schwarz FSU and SFE.

XCEIVE Inc. Nov 2005 – Aug 2011

Mixed signal RFIC designer

CMOS TV-Tuner SoC: LNA, Mixer, VCO, PLL, polyphase and IF filter design.

Transferring TV-tuner SoC from one process to another process, CAD, layout-tapeout. Designed TV-Tuner RFIC System on chip, image rejection mixer, Polyphase RF and baseband Q and I filter, 8th order Video Filter.

Transferred 4mmX4mm RFIC System on chip from JAZZ 0.18um to TSMC 0.18um

Full tape-out and verification in 4 months together with 2 more designers. Designed while library of analog cells in cadence database for UMC 0.18um process. DC-DC buck converter for RX. Audio analog Driver.

Texas Instruments 2001 – 2002 -2005

Audio Baseband CODEC design:

Design SC audio amplifier 120dB DR, 30uVrms input referred noise

Design speaker amplifier 120dB DR, output impedance 8 ohm, 16 ohm, 32 ohm with 10different speaker RLC models

Design Audio SC DAC 120dB DR, and Audio Delta Sigma ADC 21bit

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