Design Engineer Layout

Aniva Boone

Imperial Beach, CA ***** 619-***-****

*************@*****.*** www.linkedin.com/in/aniva-boone

Mask Layout Designer

Accomplished and energetic with a solid history of MIPI DSI / CSI Cell and SerDes Block Support, CPR and CPR_PM Multiple IPs Release Support, and Anti-glitch Support Samsung 5nm FinFET within deep sub-micron industry. Skilled in troubleshooting and understanding technology process nodes. Creative and collaborative, known for effective project leadership and diligence. Strive to exceed expectations. Cross-functional communicator, adept at effective time management. Also, expertise Ribbon-FET DRCs, LVS, ANTENNA and DENSITY checks.

Technical & Specialized Skills

Cadence Virtuoso VXL UNIX CMOS Layout Design Analog Mixed Signal Integration

Caliber DRC / LVS / ERC / SOFTCHECK Analog Mixed Signal Layout Design

LEF / DEF Syntax DesignSync Assura version av4.1 Physical Verification Systems

MEMS Layout Design Cliosoft SOS

Professional Experience

BOEING, HUNTINGTON BEACH, CA

Experienced Mix-Signal Layout Designer May 2023 Present

Responsible for research and development with testcases of new and innovating technology process nodes such as GAA (Gate All Around) or RibbonFET. Also, continuous floorplanning, P/G routing, signal routing, DRC, LVS, layoutXL compliant and Antenna clean. Delivering sub-blocks or major blocks (within GF12lp or intel18A) in a timely manner. Using Caliber tool for coloring and fill process. Using best layout practices such as common-centroid for matching or symmetry. Build layout structures, antenna FETs, via-chains with different metal layers, power-via cells, PCM diodes, primitive structures, etc.

WISPRY, Irvine, CA

Senior Layout Designer September 2020 --- March 2023

Responsible for delivering top-level chip such as CMOS integrated with MEMS layout with high voltage drivers. Made sure that the top-level chip was DRC/LVS/ANTENNA/DENSITITY clean. Also, meet ESD specifications with pads and ESD structure cells. My main objective or function was to be able to deliver chip(s) or sub-blocks to get it DRC/LVS/ANTENNA/DENSITITY clean for preparation of tapeout. Using technology process nodes of 180nm or 65nm.

Assembled RETICLE plans with chip die cells for tapeout. Worked with MEMS designers and RF layout designers of the structures of the MEMS beams. Also, debugged any DRC/LVS issues with a specific die cell.

Responsible working on versions of RF SOI switch design chips. Implementation of CMOS controller block with larger series/shunt FETs. Also, made sure to protect high sensitive signals (shielding or distance keep-out region). Troubled-shooted any DRC/LVS/ANTENNA/DENSITITY issues. Also, fixed any “red flag” issues from the foundry.

Assembled series/shunt FETs for RF SOI Switch Chip. Worked with the circuit designer for desired “tuning capacitance”. Made sure DRC/LVS clean.

Debugged MIPI digital blocks by various different projects from Physical Design teams. Sanity checks such as DRC/LVS. Edited layouts & CDL or spice netlist to get a stand-alone LVS clean to accommodate Cadence tools.

Floorplanned and compacted CMOS control logic block for updated version of RF SOI switch chip. Also, worked with the circuit designer with other sub-blocks.

Generated ESD structures for the RF SOI Switch Chip. Made sure robust connections for the anode and cathode.

WINMAX., Sunnyvale, CA

Analog Layout Designer May 2020 – June 2020

Responsible for delivering digital layout block using TSMC 5nm FinFET design layout rules. This digital layout block is implemented within the REFGEN CLOCK top block. The block’s name is called msn5_cmn_refgen2_core_dig. Responsible implementing ports using the pin placement feature and using multiple patterening tools to check for coloring violations. Also, made sure the block is Caliber DRC & Caliber LVS clean.

ENCORE SEMI INC., San Diego, CA

SerDes IP Layout Designer March 2019 – August 2019

Responsible for delivering single or multiple cell layout blocks for the client’s (Samsung) SerDes team. My main function or objective goal is to deliver cell blocks that are Caliber DRC and LVS clean within the Samsung 14nm FinFET environment.

Assembled high-speed digital cell blocks for the receiver (RX) SerDes. Generated floorplan (Caliber DRC clean), detail routing and verification within Samsung 14nm FinFET environment. Matching high-speed signals such as clock signals.

Implemented floorplan strategy on analog cell blocks (current mirror) for the transmitter (TX) SerDes. Apply matching routing and verification (Caliber DRC/LVS/ERC) on analog cell blocks.

Gained extensive knowledge on Caliber DRC and LVS tool settings. Apply certain settings to within Caliber to troubleshoot verification issues.

Prepared P&R blocks within the main BIAS block. The purpose of this integration is to make P&R blocks more VXL compatible and maintain LVS clean. Achieved in DRC, LVS & ERC clean BIAS block.

Achieved implementing power gridding on BIAS block to improve IR-drop issues. Working closely with engineer to improve power gridding of BIAS block.

QUALCOMM INC., San Diego, CA

Staff Mask Layout Designer 1999 - 2018

Accountable for delivering single or multiple IPs to company's customer engineers for chip-level tape-outs. Coached and mentored other mask layout designers to achieve primary goal. Worked both independently and collaboratively. Led 4 - 6-member team in releasing multiple IPs.

Generated standard cell templates for analog and digital sections (general, thick, analog, thick analog) for both CSI and DSI libraries. Implemented layout design rules for TSMC 28nm. Fixed DRC / LVS / ERC issues for critical blocks used in the SerDes Layout team in Qualcomm.

Performed top-level integration on multiple IPs for the Istari V3 CPR Samsung 14nm FinFET. Enforced certain serpentine structures (C7) not to have underneath other serpentine structures (K1 or C6).

Led a team of 3 to generate 2 versions of analog blocks for the top-level integration of Jacala / Istari Prime CPR Samsung 14nm FinFET. Troubleshooted ERC issues and fixed low-density RX recommended design rules.

Assembled NAND, NOR, MUX oscillators, wire-ROs, age sensor, head switch, and gator mux oscillator for Soundwave / Jacala Samsung 10nm FinFET / Samsung 14nm FinFET. Verified top-level IPs and implemented DFM checks to check the integrity of these 5 CPR IPs (cpr3_hd, cpr3_hd_ls, cpr3_hp, cpr3_hp_ls and cpr3_pkgstress). Generated LEF files for CPR IPs for chip-level.

Integrated HD and HV standard cells within the same analog layout blocks and delivered the analog blocks in a timely manner. Executed numerous Caliber DRC trials to test the design limitations for the CPR WTR8K Samsung 14nm FinFET.

Generated GDS files, CDL files, Redhawk data files and layout database for CPR and CPR_PM for Hana V2 TSMC 7nm FinFET. Assisted in IR drop analysis by implementing more power and ground via connections.

Led a team of 3 to 4 mask layout designers that delivered multiple analog blocks for CPR and CPR_PM for Hana V2 / Poipu V2 TSMC 7nm FinFET. Generated GDS files, CDL files, Redhawk data files and layout database files.

Implemented DRC / LVS / ERC / SOFTCHECK and DFM checks for sub-blocks for anti-glitch support in Samsung 5nm FinFET. Implemented common-centroid, matching, and shielded critical nets.

Lead a team of 3 mask layout designers to fix single diffusion break (SDB) issues within the analog blocks of Soundwave / Jacala Samsung 10nm FinFET / Samsung 14nm FinFET by implementing filler cells. Also implemented a via redundancy check to make sure that the analog blocks have enough metal enclosure percentage. This action resulted in a clean DFM database.

Education

Bachelor of Science (BS), Electronics of Engineering of Technology,

DeVry University, Long Beach, CA

Specialized in Analog RF Layout Design / Digital Designs, UNIX Syntax, Mathematics

Professional Development

Self-taught TSMC 7nm FinFET layout design rules

PERL class, Q-Learn, San Diego, CA

Samsung 10nm FinFET course, Q-Learn, Online

Samsung 14nm FinFET course, Q-Learn, Online

PDCAD class for TSMC 7nm rules, Q-Learn, San Diego, CA

Attended Silicon Ensemble / First Encounter (Place & Route) course, Cadence Inc., San Jose, CA

Awards

Recognized with company Qualstar award for contribution to lesser sensor initiative and pushing it through BlueStreak V1 in 2018

Earned Qualstar award for excellent contribution in delivering quality 10nm CPR sensor IP in production in 2017

Awarded Qualstar recognition for supporting CPR and CPR_PM sensor layout design and integration on multiple 10nm projects in 2016

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