Design Engineer Senior Staff

Hayk Mamikonyan

Mobile: +374-********

Email: ***********@*****.***

I am Permanent Resident of Canada, will relocate to Canada in May Work Experience

**** *** – till now Synopsys Armenia SG, Chip Design IT Company IPG, IP Group

ASIC Physical Design Engineer, Senior Staff Engineer

• Working on DDR testchip products: developing PNR, EM/IR flows

• Working on Ethernet Subsystem and SerDes PHY projects

• Timing/congestion closure of ASIC blocks

• Design tapeouts in 7nm or below process technologies

• Design from netlist to GDS including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Timing closure, physical verification and EMIR

• Developing and implementing timing ECOs

• Developed flow for RedHawk_SC runs (EM, IR, RampUp)

• Supporting RTL to GDS design flow improvement to meet digital design challenges

• Working on migration of design flow from ICC2 to Fusion Compiler

• Experience with Synopsys design/verification tools and flows

• UNIX and scripting programming skills (Python, TCL, Perl, shell)

2011 – 2022 Synopsys Armenia SG, Chip Design IT Company Special IO department

A&MS Circuit Design Engineer, Sr II

• Top level verification for analog and digital blocks

• EM & IR simulations for analog blocks

• Power number generation for databook

• Current profile generation for PI analysis

• Enhancement of scripts (to speed up and improve setup and reporting)

• Adopting top level verification flow for new protocols and products

• Developed test plan and checklist documents for top verifications

• Project planning and scheduling

2007 - 2011 Synopsys Armenia SG, Chip Design IT Company Analog and mixed signal department

A&MS Circuit Design Engineer, Sr II

• Design and porting of sub cells of analog blocks: TX, RX, PLL, RTUNE

• EOL (End of life) simulation flow development

• Scrips improvement for report generation

2004- 2005 Synopsys Armenia SG, Chip Design IT Company Analog and mixed signal department

Analog Engineer

• Design and porting of sub cells of analog blocks: PLL, Lock detector, DLL, ADC, DAC

2002 –2004 LEDA Design Inc, Chip Design IT Company Analog Engineer

• Design and porting of sub cells of analog blocks: PLL, ADC, DAC, VREG, Bandgap

Education

2003-2005 State Engineering University of Armenia, Computer Systems and Informatics Department (Synopsys Armenia) / Master’s degree

Specialization “Technology and Design of Integrated Circuits”.

Diploma Work “Research and Design of Full Digital PLL” 1999-2003 State Engineering University of Armenia, Computer Systems and Informatics Department (Synopsys Armenia) / Bachelor’s degree

Specialty “Design and Technology of Electronic-Computing Devices”

Specialization “Microelectronic schemes and systems”

Diploma Work “Design of 1.5bit mdac”

Certificates

Certificate in recognition of successful completion of C++ training (level1,2), organized by MICROSOFT INNOVATION CENTER

Certificate in recognition of successful completion of C# training (level 1,2), organized by MICROSOFT INNOVATION CENTRE

Relevant Skills

Deep understanding of analog circuits functionality Analog blocks design at sub-micron technologies /down to 10nm. Design of analog parts of USB

Knowledge of Python, Perl, Tcl scripting languages Knowledge of C++, C# programming languages

Work experience with Perforce

Other Skills

MS Office (Word, Excel, PowerPoint, Visio)

Windows, Unix (Linux, SUN)

Tools: DesignComiler, ICC2, FusionComiler, PrimeTime, ICV, Calibre, Microsoft Visual Studio, Cosmos, Custom Designer, Hspice, ViewDraw, SmartSpice, DVE, WaveView Language Skills

Armenian, Russian (native)

English (upper intermediate)

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