Verification Engineer R D

Qaisouni Babikir SUMMARY

Analaytical Design and Verification Engineering professional with experience in architecting multi-layered reusable Self-Checking Testbench Environments. Effectively created Verification plans, developed Verification Environments using Bus Functional Models, Transactors, Monitors, Assertions and Checkers, Design Debugging and Issue Tracking for Unit and Block Level Verification as well as ASIC Verification to reach Coverage Goals. Proven success in enhancing existing systems with new features and performance improvements. Core strengths in:

• Verification Partitioning and Development Flow

• Directed and Coverage Driven Random Verification Flow

• I/O Protocols and Controllers Verification

TECHNICAL SKILLS

Methodologies and UVM,System Verilog (SV), Verilog, System Verilog Assertion (SVA), C/C++, Unix/Linux, Tcl Languages Perl scripting and Python.

Simulators VCS, Xcelium simulator, Verilog XL, Modelsim, Tools JASPER, VMANAGER, Verisium_Debugger and IMC. Protocols APB, AHB, ACE, AXI and CXL

PROFESSIONAL EXPERIENCE

• Senior Verification Engineer R&D August 2020– October 2024 Netlist

Built UVM test bench for device coherency module. The coherency model connects to host via Computer Express LinK . The coherency module ensured memory coherency of all the agents caches also point of coherency and serialization. The UVM test bench was constructed including agent, driver, sequencer, monitor, environment, test, Topmodule, Sequences and Register abstraction model. Verification plan was tabulated and functional coverage achieved 100%.

• Senior Verification Engineer R&D October 2019– July2020 ACUTUS

Built UVM complete test bench from scratch Block level verification environments for two FPGAs STRATIX V. Built the agents environments, tests, top_module and test cases to achieve 100 % functional coverage. Also wrote the verification plan from the design requirement.

• Design and Verification Engineer October 2018 – October 2019 L3 Harris

created UVM chip level verification environments for multiple FPGAs Developed reusable agents and top level test bench modules and environments .FPGA verification using complete UVM test bench and assertions. Functional coverage to achieve 100% coverage. verification of control and data plane functionality.

Sram memory design. 4 transistors SRAM memory cell. Sram design in both sytem verilog and vhdl. Sram was verified using UVM test bench, also a memory controller was verified by selecting different SRAMs and writing and reading to them. Verified Memory controllers for DRAM and Flash memories connected o the processor via AMBA buses connecting the processor to the Memory controller. Assertions were used to verify the Memory controller control path. Scoreboards were used to verify the memory controller data path. Assertions were used extensively to verify that timing requirements for SRAM, DRAM and FLASH memory were not violated.

November 2010-October 2018

• Design and Verification Engineer

Metco,

• Boeing Design Verification

• FPGA verification of space craft system through UVM testbench and environment. The system is composed of 5 FPGAs for telemetry and control. UVM test sequences were used to simulate the space craft control environment. Constrained random variables were used to test corner cases. Score boards were used to compare in and out of order transactions. UVCs encapsulating different protocols on the block and system level were developed for reuse. Functional coverage was used to verify the functionality of Design Under Test. Memory controller

• SDRAM, ROM, SRAM and Flash memory controller. Interface Design and Verification Plan Creation, RTL Designing of Controller. Read and Write signals to the SDRAM is burst oriented and start at the address specified by the AHB bus.

• Created Directed Testbench Verification Environment and Testcases to mitigate the first level of Design bugs and later enhanced this Verification Environment to demonstrate Control Transfers, burst Transfers, Interrupt Transfers and Isochronous Transfers with Control Flow and Error Injections.

• Created UVM components and test cases to separate structural from behavioral for reuse. Constrained random stimulus

were created as sequences to stimulate the DU. Driver and Sequencer were synced with the virtual interface

• Scoreboard was used for self-checking along with assertions to check corner cases.

• Developed and Debugged the various components in Constrained Driven Random Verification Environment including Generating the Constrained Random Stimulus Packets for multiple endpoints, Created and Debugged the BFM for Application Layer, Drivers, Monitors, Checkers, Scoreboards and Covergroups. Inserted System Verilog Assertions to validate the design.

• System on Chip memory System compromising of various modules written in Verilog and verified in system Verilog and finally implemented on Altera FPGA. Inter process communications between the various modules were synchronized using semaphores and concurrency. Mail boxes and call backs were used extensively for concurrency, error injections and different configurations. ASICA and FPGA design flow.

• Functional Verifications was achieved via stepping through using random constrained stimulus and corner cases by directed testing.

• Design and Verification Engineer August 2008 – November 2010 Huwawei, Santa Clara

• AMBA AHB Based Device Controller Role: RTL Design &Verification

• Created and Debugged the Various Components of Constrained Driven Testbench Environment including Random Stimulus Packet Generation for multiple endpoints, Created the BFM to control the Read and Write Operation to, Created Drivers, Monitors, Checkers, Scoreboards and Coverage Groups

• Created Directed Testcases to reach the Corner Cases using existing CRV Environment to close the Coverage holes

• RTL Debugging and enhancing the existing Device Controller’s CSR Module to support 64 bit and 128 bit read/write operation over AMBA AHB Bus. Created, Debugged and Maintained the Register Abstraction Layer

(RAL) file

• Debugged Host Model’s Protocol Layer, helped in enhancing the VIP capability to support the Control Flow Transaction

• Effectively managed the bug tracking and nightly regression databases and helped the team to meet Coverage Metrics

• ATM Switch Role: RTL Debugging and Verification

• Created Directed Verification Environment and Testcases to mitigate the first level of Design bugs and enhanced this Verification Environment.

• Wlan design verification of IEE 802.11 ac Transmitter and Receiver.

• Enhanced and Debugged the Protocol Layer of Device VIP model to support the Control Flow and Error Injections

• Effectively managed the bug tracking and nightly regression database and helped the team to meet Coverage Metrics

• Documented all the Control and Status registers, Created several directed testcases on customer’s demand to provide a template of read and write sequence for various stages of ATM Switch operations.

• Clock Domain Crossing Analysis of D20AHB Role: CDC Analysis and Assertion Based Validation

• Created the Prime Time Report to Check the CDC paths against RTL

• Analyzed the Source Clock and Destination Clock and determine the characteristics of CDC signals to identify Sync type

• Inserted System Verilog Assertions in RTL to validate Level, Pulse, Toggle, Bus and FIFO Synchronizers

• Documented the CDC paths with waveform capture for Customer Clarification

• Design and Verification Engineer February 2007 – August 2008 Innovative Technologies Inc., San Jose, CA

• Buffer Management Unit Role: Design and Verification Engineer

• Created the Design Specification as per Customer’s Specification, RTL Designing of Buffer Management Unit, Asynchronous FIFO Controller, Synthesis, Place and Route, Static Timing Analysis, Bit Stream Generation

• Created the Block Level Verification Environment in Verilog, Created directed and random Testcases to verify the basic functionality as well as corner cases of Buffer Management Unit

• Helped Customer in integrating the Buffer Management Unit with their Design and helped them in creating and debugging the System Level Verification, Pre-Silicon FPGA Validation

• Design Verification using VMM and system Verilog to achieve 100% functional coverage.

• Project AXEL-X2 Switch Evaluation Board Role: Design Specification

• Participated in writing Engineering Specification for FPGA Design, Design Partitioning, Defining Interface Signals among blocks, Multi-Clock Synchronization Schemes for Control and Data, State Machine Designing and CRC Algorithm

• FPGA selection, Implementing FPGA Design Flow using Lattice MachXO FPGA

• Participated heavily in writing Product’s User Guide EDUCATION/PROFESSIONAL CERTIFICATION

Master of Science in Electrical Engineering, San Francisco State University, San Francisco, CA Bachelors of Science in Electrical Engineering, Chico State University, Chico,CA System Verilog Testbenches and System Verilog Assertions, synopsis online training Formal Verification using Cadence JASPER

Contact this candidate