Computer Engineering Product Development

James Mareachen

Winfield, IL ***** 630-***-**** ************@*****.*** Linkedin.com/in/jmareach/

EDUCATION

Purdue University, School of Electrical and Computer Engineering West Lafayette, IN

Bachelor of Science in Computer Engineering Fall 2025

GPA: 3.97

Honors: Dean’s List, HKN Honor Society, IEEE Computer Society

Relevant Coursework: ASIC Design, Operating Systems, Data Structures, Microprocessors and Interfacing, Signals and Systems, Digital Circuit Design, Electrical Engineering I & II, Linear Algebra, Advanced C Programming

Master of Science in Computer Engineering Fall 2026

GPA: 4.00

Focus Areas: Computer Architecture, Artificial Intelligence, High-Speed Digital Design

PROFESSIONAL EXPERIENCE

JLG INDUSTRIES

Computer Engineering Product Development Intern – Connected Solutions

Hagerstown, MD

May 2024 – Jan 2025

Designed and implemented IoT hardware testing frameworks using Python and C, achieving 1,000+ engineering hours saved per quarter.

Spearheaded implementation of CAN messaging protocols, (broadcast, DM14-16, PGN), enabling real-time system communication and validation.

Debugged embedded systems and memory interfaces using oscilloscopes, logic analyzers, power measurement tools to diagnose and troubleshoot hardware.

PURDUE UNIVERSITY

Digital Systems Design TA

West Lafayette, IN

Aug 2024 – Present

Led system design labs for 500+ students, focusing on SystemVerilog, debugging, and performance optimization of FPGAs and ASICs.

Assisted students in hardware/software validation, emphasizing efficient subsystems, high-speed digital SystemVerilog-based architecture, programming, and synthesis.

TECHNICAL PROJECTS

Custom AXI5 Interface Implementation

Architected a full AXI5 interface using SystemVerilog, supporting high-speed memory-mapped communication, demonstrating expertise in HBM, DRAM, and SRAM subsystems.

Implemented comprehensive manager and subordinate modules supporting memory-mapped communication.

Conducted detailed timing optimization, debugging, and bandwidth analysis for high-speed SoC design.

TPU Architecture for High-Speed AI Processing

Designed a custom AI acceleration unit in SystemVerilog, optimizing for high-bandwidth AI workloads and parallel processing.

Implemented floating-point (bfloat16) matrix multiplication modules tailored for high-speed architectures.

Optimized pipeline architecture to maximize computational efficiency in high-memory-bandwidth environment.

Real-Time Embedded Train Controller

Developed a real-time navigation and control system for trains using STM32 microcontrollers, programmed in C for precise low-latency operations.

Integrated SPI communication facilitating Pulse Width Modulation (PWM), Digital-to-Analog Conversion (DAC), and Analog-to-Digital Conversion (ADC) to optimize speed control and system performance.

APPLICABLE SKILLS & INTERESTS

Software: SystemVerilog, C/C++, Python, Assembly, Java, MATLAB, Make, LTspice, LaTeX, R, 3D Design, Office

IDE/Compilers/Synthesis/Simulation: Yosys, Modelsim, Vivado, Virtuoso, Visual Studio, PyCharm, VIM

OS: Linux, UNIX, Windows

Hardware: ICE40, RISC-V, Oscilloscope, ASIC, FPGA, Digital Multimeter, AC/DC Power Supply, Soldering

License/Certificate: Amateur Radio License KD9HJG

Leadership/Involvement: Eagle Scout, CARS auto repair, Purdue Semiconductor Student Alliance Events Chair

Hobbies/Interests: Rock Band, Backpacking, Snowboarding

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