Fpga Engineer Electrical Engineering

Jason Huang

**** ***** ***** *****, ****** Palos Verdes, CA 90275

Mobile: 310-***-**** Email: ************@*****.***

Professional Summary

I have Over 25 years of experience in FPGA/ASIC design, verification, implementation and debugging. Starting with architecture, block diagram, RTL coding, simulation, synthesis, timing closure, bitstream and boot.bin generation, debugging the FPGA and test in the lab, scan pattern generations for ASIC, I have done all of them. Lately my FPGA work has shifted from Command and Data Handling to DSP, such as up/down-sampling, complex FIR, (I)FFT, polyphase channelizer and half-band filter. Also, at Mercury Systems, I wrote VHDL code for polynomial function to compensate amplifier distortion and reduce unintended sideband. My previous project is NVMe bridge implementation for the SSD, and encryption/decryption for the Write/Read. Also, I worked on the Xilinx Zynq Ultrascale MPSoC for AMCS FPGA project that requires transmitting and receiving the data via PCIe, 1553, I2C, I2S, UART and A429.

Education

M.S., Electrical Engineering, California State University, San Jose, CA

B.S., Electrical Engineering and Computer Science, University of California, Berkeley, CA

Computer Skills

Computer Operation Systems: Windows, Linux, Ubuntu Linux

Computer Language: VHDL, Verilog, C++, Python, Perl, TCL scripting, Matlab

Work Experience

Mercury Systems Inc (formerly Physical Optics Corporation), Torrance, CA 05/2017 – 02/2025

Firmware Engineer III

Use Xilinx Vivado and ZCU106 dev board to design, implement and verify AVIO_FPGA (Xilinx Zynq U+) and XMC_FPGA. Functional blocks are Zynq, AXI bus, PCIe, I2C, I2S, UART, 1553 and A429

Implement NVMe Bridge design for SSD on Xilinx ZCU106 dev board and Fidus Sidewinder 100

Use Bonnie++ to test the throughput for Read/Write on the SSD

Add encryption and decryption on NVMe Bridge design for Fidus Sidewinder 100

Run tests in the lab using oscilloscope, Eye Diagram scope, ILA in Vivado and C code in Linux environment

Write VHDL code for polynomial function to compensate amplifier distortion and reduce unintended sideband

Lockheed Martin, Syracuse, New York 03/2016 – 05/2017

ASIC/FPGA Engineer

Generate VHDL codes for up/down-sampling, complex FIR, (I)FFT, polyphase channelizer and halfband filter

Generate VHDL codes for digital mixer and NCO for the baseband signal

Implement RIB (Radar Interface Board) FPGA for TPQ-53 Counter Fire Target Acquisition Radar

Design and write VHDL codes for the following modules: interfaces for UDP Ethernet (1000BaseBx,100BaseT,1000BaseT), ADC and UART, Dwell Command, Time Processing for the GPS, UART.

Synthesize, place and route, and implement the FPGA in Artix 7 FPGA using Vivado tool

Schneider-Electric, Lake Forest, California 06/2015 – 03/2016

FPGA Consultant

Implement Digital Input FPGA for Trilogy Project using Xilinx Spartan6 FPGA

Synthesize, place and route the FPGA in Artix7 FPGA based on DO254 standard

Design and verify DAC/ADC interfaces for TI DAC5322/TI ADS7953 with SPI Bus

Design and verify SOE (Sequence of Events) and FVD (Forced Value Diagnosis) logics

Conduct code review using Collaborator and TFS for all modules

Integrate, simulate and debug Software/FPGA images with Atmel processor

Advanced Bionics, Valencia, California 12/2010 – 06/2015

Senior ASIC/FPGA Engineer

Designed SC90K digital block using register-based RTL coding style for low power chip

Utilized Leonardo to synthesize the VHDL code for 1- and 2-phase clocking schemes

Ran the recursive simulation at netlist level with SDF file

Wrote RTL codes (VHDL and Verilog) into Altera Cyclone IV E FPGA using Altera Quartus 12.0

Implemented DFT (Mentor Graphics Fastscan) for scan chains, generated test patterns and interfaced with fab foundry

Created and debugged test cases; generated test bench for regression test

Developed VHDL code with scan chain for quadrature receive demodulation, and performed simulations in Modelsim

Generated scan patterns using DFT FastScan and simulated the patterns in Modelsim

Parker Aerospace, Irvine, California 04/2009 – 10/2010

Hardware Engineer

Command FPGA and Monitor FPGA for EMB project – developed for balancing the airplane

Write VHDL and test FPGA with software team in the lab

Northrop Grumman Aerospace Systems/TRW, Redondo Beach, CA 2001 –2009

Senior Member of Technical Staff/Project Lead

Received Recognition Award for the successful completion of the Telemetry FPGA IDR3 and PDR

Battery Discharged Unit (BDU) FPGA Project

HAL ASIC Project (for AEHF Phased Array Antennae)

Texas Instruments Inc., San Diego, CA 2000 – 2001

ASIC Engineer

ASIC Design/Application Engineer – PRIMA ASIC

Raytheon Missile Systems, Tucson, AZ 1999 - 2000

Hardware Engineer - CHAMP ASIC (AMRAAM Phase III Missile)

ASIC design, write VHDL code, DFT scan insertion

write behavior VHDL code for FFT for verification

Real 3D Inc., Orlando, FL 1997-1999

ASIC Design Engineer

ASIC design, write VHDL code for libraries for Cobra ASIC and Sega ASIC

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