Physical design engineer

RESUME

Name : Chandrasekharachari. S

Email id :**********.*****@*****.***

Phone : +91-950*******

Summary:

• Worked as Physical Design engineer at Agasthya App Labs Pvt Ltd from July 2022 to till June 2023.

• Have 1year internship experience on VLSI Physical design in Sion semiconductors, Bangalore from july 2019 to july 2020.

• Have 1.2 years of experience as Associate analyst from GlobalLogic technologies from 2017 nov to 2018 dec.

• Good knowledge in Floor planning, Placement and Routing, Clock tree synthesis, routing and basics of STA.

• Worked on 28nm and14nm technology.

• Good experience in ASIC Physical Design.

• Experience in ASIC backend design Floor planning, Power plan, Placement, CTS, routing, DRC clean up.

• Resolving various Block level PnR issues.

• Highly adaptable to all kind of environment.

• Always on the look to improve Skills and grow with Organization

• Technical Expertise

• Tools : Synopsys ICC I, ICC II, Innovus,

• Scripting languages : TCL, PERL

• OS Platforms : Windows, Linux

Project Details:

Project 1: hdl_cell001_line16

Description: This project was a Block-level design implemented in TSMC 14nm, the block was around 560k gates with 62 Macros, the frequency of the block is 710Mhz. Roles and Responsibilities:

• Block level implementation of Floor planning, Physical Cells, Placement, CTS and routing.

• The Utilization of the block was 70% which Leaded to highly congested design.

• Placing macros and applying blockages play a key role.

• Congestion and timing issues there because of High instance count with Lesser area during Placement stage.

• Cleaned Logical DRCs like Max Cap, Max Trans, and Timing Issues. Challenges:

• Analyzing the cell placement and preparing a recipe to get congestion free placement.

• Meeting CTS goals with different techniques.

• Fixed DRV's violations, DRCs issue and Antenna violations.

• Tried multiple Floor-plan to getting good placement and tried different technique like placement blockages, cell padding, etc. to get congestion free design.

Project 2: hdl_cell001_line32

Description: This project was a Block-level design implemented in TSMC 28nm, the block was around 200k gates with 73 Macros, the frequency of the block is 550Mhz. Roles and Responsibilities:

• Block level implementation of Floor planning, Physical Cells, Placement, Post Placement Timing Closure, Congestion analysis.

• Clock Tree Synthesis, Post Clock Tree Synthesis Timing Closure, Routing.

• Fixing DRCs.

Challenges:

• Analyzing the cell placement and preparing a recipe to get congestion free placement.

• Meeting CTS goals with different techniques.

• Fixed DRV's violations, DRCs issue and Antenna violations.

• Tried multiple Floor-plan to getting good placement and tried different technique like placement blockages, cell padding, etc. to get congestion free design.

Academics

• Completed B.Tech in E.C.E at SSIET, Nuzvid from JNTU Kakinada –2016 with 67%.

• Completed Diploma in ECE at AANM & VVRSR Polytechnic from Gudlavalleru – 2013 with 80%.

• Completed S.S.C from Sri Chaitanya Public school from Vissannapeta – 2009 with 74% Declaration:

I hereby declare that the information furnished above is true and correct to the best of my knowledge. Date: Signature

Place:

(S.CHANDRASEKHARACHARI)

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