Design Engineer Layout

RAGHAVENDRA

Professional summary:

Principal Layout Design Engineer with 13.7 years of experience in designing high-quality layouts for critical analog, memory, and standard cell circuits. Extensive expertise in semiconductor layout design across multiple technology nodes and foundries. Adept at collaborating with circuit designers to meet performance targets and enhance manufacturability. Proficient in mentoring teams and driving innovation to deliver high-performance IC solutions aligned with organizational goals. Technical Skills:

● Technology nodes: 6nm, 7nm, 14nm, 16nm, 28nm, 40nm, 55nm, 90nm, and 180nm.

● Foundries: TSMC, Samsung, Micron, and Global foundry.

● EDA Tools: Cadence Virtuoso XL/L, Calibre, Cadence Pegasus, VOLTUS, and ParagonX.

● Verification Expertise: DRC, LVS, Antenna, Latch-up, EM/IR Analysis, Parasitic Analysis.

● Specialized Skills: Area optimization expert, High current metal planning, IR drop analysis, Analog array matching, Parasitic analysis, and Chip level verification.

● Leadership Skills: Strong project management and mentoring expertise. Professional Experience:

● Principal Engineer at Microchip Technology, India (June 2021 – Present).

● Senior Engineer at Micron Technology (March 2019 to June 2021).

● Technical Leader at Aricent Technologies Holdings Limited (March 2018to March 2019).

● Staff Engineer at Black Pepper Technologies (January 2017 to February 2018).

● Analog Layout Engineer at Omniphy India Private Limited (Acquired by NXP)

(February 2013 to December 2016).

● Analog Layout Engineer at DRDO LAB (RCI) (May 2011 to January 2013). Key Projects:

Project: Ethernet

Blocks: Pipeline ADC, PGA Test, BT Receiver, Regulators, and Bias circuits. Role:

● Successfully led layout teams, providing mentorship to ensure on-time, high-quality task delivery.

● Developed noise-immune layouts and resolved latch-up issues.

● Ensured precise matching for analog array devices, and enhanced metal stack plans to meet high- current needs.

Project: SERDES (PCIE I and II, SGMII, and V-By-One) Blocks: Transmitter, Regulators, and Bias circuits. Role:

● Led the layout development, ensuring alignment with design constraints and achieving symmetrical routing and analog array matching.

● Created latch-up immune layouts, addressed EM and IR drop challenges, and implemented parasitic reduction techniques for improved performance. Project: USB 2.0

Blocks: Transmitter, Regulators, and Bias circuits. Role:

● Implemented circuit design constraints to layouts, ensuring compliance with post-layout specifications.

● Designed complex high current metal plans for drivers.

● Resolved EM, IR drop issues and critical parasitic constraints to enhance design robustness.

Project: DRAM and HBM

Blocks: Reference generators, Bandgap, Bias circuits, Standard cells. Role:

● Led cross-functional teams to achieve project milestones, delivering layouts with compact floor plans and efficient metal track utilization.

● Collaborated effectively with global teams to coordinate project timelines and deliverables.

● Addressed layout and foundry-related challenges effectively. Project: IO blocks and standard cells.

Blocks: OVUV, RGMII, PUPD, and standard cells.

Role:

● Designed IO layouts with a focus on compactness and optimized driver currents.

● Generated R90 layout versions, ensuring compliance with poly orientation requirements.

● Delivered compact standard cell layouts while adhering to design specifications.

Education:

● Master of Technology in Microelectronics – BITS Pilani University.

● Bachelor of Technology in Electronics and Communication Engineering – Jawaharlal Nehru Technological University, Hyderabad.

● Diploma in Electronics and Communication Engineering – State Board of Technical Education and Training, Hyderabad.

Personal Strengths:

● Adaptable and proactive learner with a growth mindset.

● Self-driven and focused on results.

● Skilled in leading teams and collaborating in diverse environments.

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