Design Verification

Bhavana Marpadaga

971-***-**** ********@***.*** linkedin.com/in/bhavana-marpadaga github.com/Bhavanareddy15 Education

Portland State University, Portland, OR Sept 2023 - Present Master of Science in Electrical and Computer Engineering GPA:3.63/4

• Coursework: Microprocessor System Design, ASIC Modeling & Synthesis, Intro to System Verilog, Computer Architecture, Pre-Silicon Validation, Assertion based Verification, SoC Design with Programmable Logic, Formal Verification

G. Narayanamma Institute of Technology and Science, Hyderabad, India Sept 2020 - May 2023 Bachelor of Technology in Electronics and Communications Engineering GPA:3.6/4 Government Institute of Electronics, Hyderabad, India Jun 2016 - Dec 2019 Diploma in Embedded Systems Engineering GPA:4/4

Projects

PvP Snake Game using Nexys A7 FPGA Verilog, C Nov 2024 - Dec 2024

• Designed a PvP Snake Game on the Nexys A7 FPGA, displayed on a VGA screen with pushbutton and keyboard controls for movement of the two snakes.

• Added a custom peripheral and modified the Wishbone interface to control the VGA display, pushbuttons, keyboard and RGB LEDs and developed an application on Catapult Studio.

• Used Xilinx Vivado to synthesize the design and generate the bitstream for FPGA programming. 8088 Bus Interfacing with the Memory and IO modules System Verilog Jan 2024 - Mar 2024

• Implemented the bus interface of 8088 with memory and IO module using interfaces for the bus functional model provided.

• Bus transactions from 8088 to the I/O and memory modules are handled using Chip select logic, Latches, Tranceiver and FSM modeling

Design and Verification of Asynchronous FIFO System Verilog/ UVM May 2024 - Jun 2024

• Implemented synchronizers and handlers that use gray code pointers in the RTL design of the FIFO to reduce the probability of metastable states.

• Created a Test Plan and a Testbench using UVM architecture with constrained randomized tests. Verification of Direct Mapped Cache Controller Formal Tools, System Verilog Oct 2024 - Dec 2024

• Ensured functional correctness of the direct-mapped cache controller across all possible scenarios.

• Utilized Synopsys VC Formal tools for exhaustive property checks and X-propagation analysis. DEC Alpha 21264 Branch Predictor C++ Jan 2024 - Apr 2024

• Simulated DEC Alpha 21264 branch predictor for the framework provided with 95% accuracy

• PC and the actual branch outcome is utilized to update the local and global history of branch predictions to predict the next branch outcome.

DDR5 Memory Scheduling Algorithm C Oct 2023 - Dec 2023

• The Memory Controller fetches the memory requests from the processor, schedules them and issues appropriate DRAM commands(Precharge/ Activate/ Read/ Write) to the DIMM.

• Implemented open page policy for DDR 5 Memory Module that generates DRAM commands without any Timing Violations. Technical Skills

Languages: System Verilog, Verilog, C, C++, Python, TCL, Matlab, Assembly: 8086, 8051, ARM, PIC, RISC V, MIPS Methodology: UVM Operating System: Windows, Linux

Concepts:Digital Logic Design, register-transfer-level (RTL), Static Timing Analysis, System Verilog Assertions, Randomization and Constraints, Code/ Functional Coverage, Formal Verification, Hardware Debugging, Processor Architectures, DDR Memory, Caches, Cache Coherence, MESI, Pipelining and Scheduling, Branch Prediction Tools: VC Formal, Questasim, Xilinx Vivado, Mentor Graphics, Pspice, Catapult Studio Lab Equipment: Oscilloscope, Function Generator, Multimeter, Soldering Experience

Failure Analysis Intern Electronics Corporation of India Limited [ECIL] May 2019 - Dec 2019

• Collaborated with the manufacturing team to identify failures, implement corrective actions, and enhance yield rates.

• The assigned responsibilities covered multiple stages of production, including Visual-Inspection, Debugging, Functional Testing, In-Circuit Testing, and Calibration of Energy Meters. Training

Basic Static Timing Analysis v3.0 Cadence Learning and Support Sept.

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