Design Engineer

Kevin M. Rishavy

**** ********* ****** *****, ******** Springs, CO 80906

Home: 719-***-**** Cell: 719-***-****

LinkedIn: Kevin_Rishavy Email: ********@*******.*** Expertise in digital ASIC and FPGA design, analog design, and PCB design Extensive experience in the electronics industry

Adept at solving complex problems, and working projects from concept to production Delivering high-performance solutions by collaboration with cross-functional teams and clients Competencies

Digital ASIC/FPGA Design System Verilog, VHDL, Verilog HDL PCB Design and Verification Team Leadership & Mentoring Analog/Mixed-Signal Design Cross-functional Team Coordination SAS/SATA, PCIe, NVM Express Emulation, Debugging, and RTL Development Experience

Microchip Technology __(2022-present)

Senior Technical Staff Engineer - Design

Develop high complexity, high-reliability SAS/SATA controller/expanders.

Lead SAS/SATA protocol processor design, managing a team of engineers, including hiring, mentoring, and performance reviews.

Debug and fix production RTL code, firmware, and custom processor code.

Coordinate RTL development and verification across global sites (San Jose, Bangalore). SEAKR Engineering __(2020-2022)

Senior Electrical Engineer

Architected and implemented JESD204B/C high-speed serial interface for satellite communications.

Designed 10Gkr interface on Xilinx Versal and UltraScale Kintex KU060 FPGA.

Served as technical lead for build-to-print module and unit test of satellite telemetry processor. Microelectronics Research & Development Corporation (COVID-19 Layoff) __(2019-2020) Design Engineer II

Designed radiation-hardened circuits with SEU, SET, and TID mitigation for high-reliability applications.

Developed radiation-hardened DDR3/DDR4 memory controller and 512Mbit flash projects. Viking Enterprise Solutions - A Division of Sanmina Corporation (2015-2019) Senior Systems Engineer

Developed high-capacity rack-mount storage (servers) from concept to high-volume production.

Managed PCB design, FPGA selection, RTL design, and system verification.

Provided on-site manufacturing support and collaborated with cross-disciplinary teams. Avago Technologies (formerly LSI Corporation) (2012-2015) Principal Design Engineer

Emulated next-generation RAID On Chip (ROC) controller using custom Altera FPGA arrays.

Conducted lab debugging and drove power reduction initiatives for RAID storage products. Earlier Career Experience (1984–2011)

Senior engineering roles at ON Semiconductor, Marvell Corporation, Intel Corporation, Ford Microelectronics, Philips, and Honeywell.

Full details available on request

Key contributions:

o Designed high-speed ADC/DAC evaluation boards and FPGA-based burn-in PCBs. o Developed ARM Cortex-M3-based ASSP-SOC and analog front-end (AFE) designs o Patented active deassertion I/O pad for SCSI and contributed to LTE R&D programs Education

MSEE — University of Colorado, 1990

Thesis: Design and Analysis of a Data Conversion ASIC for CD-ROM BSEE — University of Colorado, 1985

Certifications & Coursework

- Microchip Leadership Courses – Leading Teams

- Design and Synthesis using Verilog HDL – University of Colorado

- Analog IC Design – University of Colorado

- SAS and SATA Architecture – KnowledgeTek

- PCI Express 2.0/3.0 Architecture – MindShare

- NVM express/AHCI – MindShare

Skills

- **Design & Simulation:** Verilog, VHDL, Xilinx, Altera, Cadence Allegro, Mentor Pads

- **Programming:** C, C++, Perl, TCL/TK, Assembly (Intel-8085, ARM)

- **Tools:** Synopsys VCS, Modelsim, MatLab, HSpice, PowerArtist, PCIe Protocol Analyzer Patents & Awards

“Queued Port Data Controller for Microprocessor-based Engine Control Applications” U.S. Patent: 6,427,180 - July 30, 2002 U.S. Patent: 6,381,532 - Apr. 30, 2002

"CMOS Driver for Fast Single Ended Bus"

U.S. Patent: 5,576,640 - Nov. 19, 1996

“Pipelined Combination and Vector Signal Processor” U."Apparatus S. Patent: and 5,303,Method 172 - for Apr. Performing 12, 1994 Digital Signal Processing" Canadian Patent: 1,308,488 - Oct. 6, 1992 European Patent: B1112662 - Mar. 22, 1989 Intel - Divisional Recognition Award – Q4, 2004

“Providing Maxon with a Platform Solution to the Manitoba 32KHz Oscillator Issue” Intel - Spontaneous Recognition Award – June 20, 2003

“In recognition of contributions to bringing up ChipWatcher capability in Manitoba” Intel - Divisional Recognition Award – Q1, 2003

“Eastward Gasket Architecture, achieving better than expected performance in Manitoba”

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