Power Electronics C++

UTHRA MADHAVAN

Gainesville, Florida +1-352-***-**** *************@*****.*** https://www.linkedin.com/in/uthra-madhav/ EDUCATION

Master of Science Electrical and Computer Engineering University of Florida (CGPA: 4.0/4.0) Aug 2024-May 2026 Master of Technology Power Electronics and Drives Vellore Institute of Technology (CGPA: 3.91/4.0) Jul 2013-Jun 2015 Bachelor of Engineering Electrical and Electronics Engineering Anna University (CGPA: 3.5/4.0) Aug 2009-Apr 2013 Coursework: Computer Architecture, VLSI Circuits and Technology, Reconfigurable Computing, CAD for Hardware Security, Semiconductor Devices Fabrication, Digital Electronics, Microprocessors & Microcontroller, Power Electronics TECHNICAL SKILLS

Hardware Descriptive Languages & Methodology: System Verilog, Verilog, UVM, System Verilog Assertions, VHDL Programming & Scripting Languages: C/C++, Python, TCL, CUDA, MATLAB, Object Oriented Programming Simulation/Design Tools: Xilinx Vivado, EDA Playground, Cadence JasperGold, Synopsys VCS, VS Code, Cadence Virtuoso Operating System: LINUX, UNIX, Windows, MacOS

Domain: ASIC Design and Verification, Computer Architecture, Logic Design, VLSI Design, Circuit Design, Transistor Level Circuit Design, GPU Architecture, Digital Logic, Hardware Design, Stakeholder Communication, Cross-functional collaboration ACADEMIC PROJECTS

Design and Security Verification of Finite State Machine for Side Channel Attack Mitigation

• Designed an FSM and verified its functionality by developing the testbench architecture, coverage groups, and cover points, achieving 100% functional coverage.

• Developed coverage properties and verified them with Cadence JasperGold tool, generating assertion and bind files for both formal and functional verification.

• Analyzed Deadlock and Livelock conditions for the FSM using the SuperLint App in JasperGold. Tools & Languages: System Verilog, System Verilog Assertions, Cadence JasperGold, RTL Design Design and Functional Verification of 2 Multiple Bus Controller

• Constructed a class-based layered testbench, incorporating generator, driver, monitor and scoreboard to create transactions.

• Implemented cover group directives and cover points to track and record functional coverage. Tools & Languages: System Verilog, EDA Playground

RTL Design and Implementation of a 5-stage Pipelined RISC-V Processor

• Designed the architecture of the processor, including the five pipeline stages, data path, control unit, register file and memory.

• Built and implemented a microarchitecture incorporating control signal generation, ALU operations, data forwarding mechanisms, and hazard detection logic.

Tools & Languages: Verilog, Xilinx Vivado

Design and implementation of 256-bit SRAM Block

• Engineered and simulated a functional 16x16 6T SRAM cell capable of reading, writing, and storing 256 bits of data.

• Evaluated the read/write access times of individual cells and analyzed the propagation delay of each component. Tools & Languages: Cadence Virtuoso, CMOS transistor Development of a Cache Simulator Implementing Fundamental Cache Coherence Protocols

• Programmed a cache coherence simulator supporting MSI and MESI protocols for a multiprocessor system with individual L1 caches.

• Evaluated and compared the performance of various protocols by analyzing metrics such as miss rate and memory transactions. Tools & Languages: C++, Visual Studio Code

WORK EXPERIENCE

Assistant-Chennai Metro Water Supply and Sewerage Board, Chennai Sep 2019-Aug 2024

• Collaborated on the design, commissioning, and integration of Variable Frequency Drives for a $175.20 million USD desalination plant, supporting 15 engineers in maintenance and reporting.

• Enhanced plant operations through the integration of a Digital Control System with SCADA technology, centralizing data across 5 production lines, expediting response times and enhancing operator efficiency by 30%. Programmer Analyst-Cognizant Technology Solutions, Chennai Sep 2015-Feb 2019

• Delivered over 10 .NET applications optimized for the insurance sector, ensuring seamless functionality and operational efficiency.

• Engaged with clients to gather insights, identify requirements, and implement enhancements, boosting user experience by 25%. Project Trainee-Robert Bosch Engineering and Business Solutions, Bangalore Dec 2014-Jun 2015

• Created a MATLAB Simulink model to analyze traction battery discharging characteristics, cutting measurement errors by 20% and speeding up result interpretation.

• Optimized output voltage regulation techniques, reducing simulation time by 30% ensuring compliance with power system standards.